tda9981bhl NXP Semiconductors, tda9981bhl Datasheet - Page 8

• Manufacturer Part Number: tda9981bhl
• Description: Hdmi Transmitter Up To 150 Mhz Pixel Rate With 3 ? 8-bit Video Inputs And 4 ? I 2s-bus With S/pdif
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Functional description
TDA9981B_1
Product data sheet
8.1 System clock
8.2 Video input processor
The TDA9981B is designed to convert digital data (video and audio) into an HDMI or a
DVI stream. This HDMI stream can handle RGB, YCbCr 4 : 4 : 4 and YCbCr 4 : 2 : 2. The
TDA9981B can accept at its inputs any of the following video modes:
It can also handle audio. The TDA9981B can accept at its inputs any of the following audio
buses:
The clock management is based on a set of two PLLs that generate the different clocks
required inside the chip:
The TDA9981B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0].
The TDA9981B can reallocate and swap each of the 3 input channel ports by inverting the
bus and swapping each port.
The TDA9981B can be set to latch data at either the rising or falling edge or both.
The video input formats accept (see
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RGB
YCbCr 4 : 4 : 4
YCbCr 4 : 2 : 2 semi-planar
YCbCr 4 : 2 : 2 ITU656 and ITU656-like
I
S/PDIF (1 channel): L-PCM (IEC 60958) or compressed audio (IEC 61937)
PLL double edge can generate a clock at twice the VCLK input frequency to capture
the data at the video input formatter.
PLL serializer is a system clock generator, which enables the stream produced by the
encoder to be transmitted on the HDMI data channel at ten times the sampling rate or
more; see
RGB
YCbCr 4 : 4 : 4 (up to 3
YCbCr 4 : 2 : 2 semi-planar (up to 2
YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1
2
S-bus (4 lines): up to 8 audio channels
Section
8.14.2.
Rev. 01 — 4 July 2008
8-bit)
Table
12-bit)
5):
150 MHz pixel rate HDMI transmitter
TDA9981B
12-bit)
© NXP B.V. 2008. All rights reserved.
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