tda9870ah NXP Semiconductors, tda9870ah Datasheet - Page 35

• Manufacturer Part Number: tda9870ah
• Description: Digital Tv Sound Processor Dtvsp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10.3.2
Table 15 Subaddress 1 (note 1)
Note
1. The default setting at power-up is 11000000.
1999 Dec 20
7 (MSB)
0 (LSB)
Digital TV Sound Processor (DTVSP)
BIT
6
5
4
3
2
1
G
ENERAL CONFIGURATION REGISTER
AGCSLOW
CLRPOR
AGCOFF
SIFSEL
P2OUT
P1OUT
STDBY
NAME
INIT
VALUE
1
0
1
0
1
0
1
0
1
0
1
0
This bit controls the general purpose input/output pin P2. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0).
This bit controls the general purpose input/output pin P1. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier
in designs that employ such a trap.
The TDA9870A is in the standby mode. Most functions are disabled and power
dissipation is somewhat reduced, but the analog selectors/matrices remain
operational to support analog copying from SCART-to-SCART.
The TDA9870A is in normal operating mode. On return from standby mode, the
device is in its Power-on reset mode and needs to be re-initialized.
Causes initialization of the TDA9870A to its default settings. This has the same
effect as a Power-on reset. If there is a conflict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.
Automatically reset to logic 0 after initialization. When set to logic 0, the
TDA9870A is in normal operating mode.
Resets the power fail detector to LOW.
This bit is automatically reset to logic 0 after bit POR in the device status register
has been reset.
A longer decay time is selected for input signals with strong video modulation
(intercarrier). This bit only has an effect when bit AGCOFF = 0.
Selects normal attack and decay times for the AGC.
Forces the AGC block to a fixed gain as defined in the AGC gain register.
The automatic gain control function is enabled and the contents of the AGC gain
register is ignored.
Selects pin SIF2 for input (recommended for satellite tuner).
Selects pin SIF1 for input (terrestrial TV).
35
DESCRIPTION
Product specification
TDA9870A