tda9874aps NXP Semiconductors, tda9874aps Datasheet - Page 49

• Manufacturer Part Number: tda9874aps
• Description: Digital Tv Sound Demodulator/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.4.7
This register contains, as a binary number, the highest
subaddress used for slave receiver registers.
The first version will have the identification 0010 1101.
Table 86 Test register 2 (subaddress 252)
7.4.8
This register contains, as a binary number, the highest
subaddress used for slave transmitter (status) registers.
The first version will have the identification 0000 0111.
Table 87 Test register 1 (subaddress 253)
7.4.9
There will be several devices in the digital TV sound
processor family, with TDA9874A being the second
member. This byte is used to identify the individual family
members.
The first version will have the identification 0001 0001.
Table 88 Device identification code (subaddress 254)
7.4.10
It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g. to
incorporate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.
The first version will have the identification 0000 0010.
Table 89 Software identification code (subaddress 255)
2000 Aug 04
B7
B7
B7
B7
Digital TV sound demodulator/decoder
7
7
7
7
T
T
D
S
B6
B6
B6
B6
6
6
6
6
EST
EST
OFTWARE
EVICE
R
R
EGISTER
EGISTER
B5
B5
B5
B5
I
5
5
DENTIFICATION
5
5
I
DENTIFICATION
B4
B4
B4
B4
4
4
4
4
2 (TR2)
1 (TR1)
B3
B3
B3
B3
C
3
3
3
3
ODE
C
ODE
(DIC)
B2
B2
B2
B2
2
2
2
2
(SIC)
B1
B1
B1
B1
1
1
1
1
B0
B0
B0
B0
0
0
0
0
49
8
The digital audio interface of the TDA9874A consists of a
serial audio output and associated clock signals. It can be
used to supply digital audio signals from received
TV programs to a suitable output device, e.g. a DAC or an
AES/EBU transmitter.
Two serial audio formats are supported at the digital audio
interface, the I
MSB-aligned format. The difference is illustrated in Fig.8.
In both formats the left audio channel of a stereo sample
pair is output first, and is on the Serial Data line (SDO)
when the Word Select line (WS) is at LOW level. Data is
written on the trailing edge of SCK and read on the leading
edge of SCK. The most significant bit is sent first.
After Power-on reset, the outputs of the digital audio
interface are 3-stated to reduce EMC and allow for
combinations with other ICs. If an output is desired, it has
to be activated by means of an I
When the output is enabled, serial audio data can be taken
from pin SDO. Depending on the signal source, switch and
matrix positions, the output can be either mono, stereo or
dual language.
The Word Select output (WS) is clocked with the audio
sample frequency of 32 kHz. The Serial Clock output
(SCK) is clocked at a frequency of 2.048 MHz. This means
that there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. There are
18 significant bits used on the Serial Data Output (SDO).
A symmetrical system clock output (SYSCLK) is available
from the TDA9874A as a master clock for external digital
audio devices. After Power-on reset, the clock is off. It can
be enabled and the output frequency set via an I
command. Available output frequencies are 8.192, 12.288,
16.384 and 24.576 MHz.
I
2
S-BUS DESCRIPTION
2
S-bus format and a very similar
2
C-bus command.
Product specification
TDA9874A
2
C-bus