tda9874h NXP Semiconductors, tda9874h Datasheet - Page 19

• Manufacturer Part Number: tda9874h
• Description: Digital Tv Sound Demodulator/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.3.2
The default setting at power-up is 1100 0000.
Table 12 General configuration register (subaddress 1)
Table 13 Description of the general configuration register bits
Note
1. Bit AGCSLOW should be set to logic 1 for best possible audio performance.
2000 Jun 26
Digital TV sound demodulator/decoder
P2OUT
BIT
7
7
6
5
4
3
2
1
0
G
ENERAL CONFIGURATION REGISTER
AGCSLOW
SYMBOL
AGCOFF
SIFSEL
P1OUT
P2OUT
P1OUT
STDBY
INIT
6
General purpose I/O pins 1 and 2: these bits control general-purpose input/output pins.
The contents of these bits is written directly to the corresponding pins. If an input is
desired, the bits must be set to logic 1 to allow the pins to be pulled to logic 0 externally.
Input from the pins is reflected in the device status register (see Section 7.4.1).
Bit P1OUT is recommended to be used for switching an SIF trap for the adjacent picture
carrier in designs that employ such a trap.
Standby mode on/off: bit STDBY = 1 puts the TDA9874H into the standby mode. Most
functions are disabled and power dissipation is somewhat reduced. If bit STDBY = 0 the
TDA9874H is in its normal mode of operation. On return from standby mode, the device
is in its Power-on reset mode and needs to be re-initialized with data defined by the set
maker.
Initialize to default settings: bit INIT = 1 causes initialization of the TDA9874H to its
default settings. This has the same effect as a Power-on reset. In case there is a conflict
between the default settings and any bit set to logic 1 in this register, the bits of this
register have priority over the corresponding default setting. This bit is automatically
reset to logic 0 after initialization has completed. If set to logic 0, the TDA9874H is in its
normal mode of operation.
this bit is not used and should be set to a logic 0
AGC decay time: if bit AGCSLOW = 1 a longer decay time and larger hysteresis are
selected for input signals with strong video modulation (intercarrier). This bit only has an
effect if bit AGCOFF = 0. If bit AGCSLOW = 0 the normal attack and decay times for the
AGC and a small hysteresis are selected.
AGC on/off: bit AGCOFF = 1 forces the AGC block to a fixed gain as defined in the AGC
gain register (see Section 7.3.1). If bit AGCOFF = 0 the automatic gain control function
is enabled and the contents of the AGC gain register is ignored.
SIF input select: bit SIFSEL = 1 selects pin SIF2 for input (recommended for satellite
tuner). If bit SIFSEL = 0 pin SIF1 (recommended for terrestrial TV) is selected.
STDBY
5
INIT
4
19
3
DESCRIPTION
AGCSLOW
2
AGCOFF
1
Product specification
TDA9874H
SIFSEL
0