pca9306gm NXP Semiconductors, pca9306gm Datasheet

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pca9306gm

Manufacturer Part Number
pca9306gm
Description
Pca9306 Dual Bidirectional I2c-bus And Smbus Voltage-level Translator
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
The PCA9306 is a dual bidirectional I
enable (EN) input, and is operational from 1.1 V to 3.6 V (V
(V
The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V without the
use of a direction pin. The low ON-state resistance (R
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
In I
and bus length. Using the PCA9306 enables the system designer to isolate two halves of
a bus, thus more I
the enable pin. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517 that
provides level translation and physically isolates the capacitance to either side of the bus
even when both sides are connected.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast mode Plus I
SMBus devices.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (V
translation between higher and lower voltages selected by the user without the need for
directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.
bias(ref)(2)
2
PCA9306
Dual bidirectional I
Rev. 02 — 21 February 2007
C-bus applications, the bus capacitance limit of 400 pF restricts the number of devices
).
2
C-bus devices or longer trace length can be accommodated by using
2
C-bus. The size of these pull-up resistors depends on the system,
2
C-bus system, pull-up resistors are required to provide the logic
pu(D)
) by the pull-up resistors. This functionality allows a seamless
2
C-bus and SMBus voltage-level translator
2
C-bus and SMBus voltage-level translator with an
on
2
C-bus devices in addition to
) of the switch allows connections
ref(1)
) and 2.3 V to 5.5 V
Product data sheet

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pca9306gm Summary of contents

Page 1

PCA9306 Dual bidirectional I Rev. 02 — 21 February 2007 1. General description The PCA9306 is a dual bidirectional I enable (EN) input, and is operational from 1 3 bias(ref)(2) The PCA9306 allows bidirectional voltage ...

Page 2

... NXP Semiconductors All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD-resistant devices ...

Page 3

... PCA9306DC 306C VSSOP8 [2] PCA9306DP1 306T TSSOP8 [3] PCA9306DC1 306U VSSOP8 [4] PCA9306GM P6X XQFN8 [1] Also known as MSOP8. [2] Same footprint and pinout as the Texas Instruments PCA9306DCT. [3] Same footprint and pinout as the Texas Instruments PCA9306DCU. [4] ‘X’ will change based on date code. 4. Functional diagram Fig 1. Logic diagram of PCA9306 (positive logic) ...

Page 4

... Fig 3. Pin configuration for TSSOP8 (MSOP8) GND 1 VREF1 2 PCA9306DC1 3 SCL1 SDA1 4 002aab843 Fig 5. Pin configuration for VSSOP8 (DC1) terminal 1 index area GND 1 PCA9306GM VREF1 2 SCL1 3 Transparent top view Fig 7. Pin configuration for XQFN8 © NXP B.V. 2007. All rights reserved VREF2 6 SCL2 5 SDA2 8 ...

Page 5

... NXP Semiconductors 5.2 Pin description Table 2. Symbol GND VREF1 SCL1 SDA1 SDA2 SCL2 VREF2 EN 6. Functional description Refer to 6.1 Function table Table HIGH level LOW level. Input [ controlled by the V operation. PCA9306_2 Product data sheet Dual bidirectional I Pin description Pin ...

Page 6

... NXP Semiconductors 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Over operating free-air temperature range. Symbol V ref(1) V bias(ref)( I stg [1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V input clamping voltage IK I HIGH-level input current IH C input capacitance on pin EN i(EN) C off-state input/output capacitance io(off) C on-state input/output capacitance io(on) [2] R ON-state resistance on [1] All typical values are ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics (translating down +85 C, unless otherwise specified. Values guaranteed by design. amb Symbol Parameter Conditions I(EN LOW-to-HIGH from (input) SCL2 or SDA2 PLH propagation delay to (output) SCL1 or SDA1 t HIGH-to-LOW ...

Page 9

... NXP Semiconductors 11. Application information (1) The applied voltages at V Fig 9. Typical application circuit (switch always enabled) (1) In the Enabled mode, the applied enable voltage and the applied voltage at V Fig 10. Typical application circuit (switch enable control) PCA9306_2 Product data sheet Dual bidirectional I ...

Page 10

... NXP Semiconductors 11.1 Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to HIGH side V regulate the EN input. A filter capacitor on VREF2 is recommended. The I output can be totem-pole or open-drain (pull-up resistors may be required) and the ...

Page 11

... NXP Semiconductors Table 10. Calculated for V V pu( 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V [1] + compensate for V PCA9306_2 Product data sheet Dual bidirectional I Pull-up resistor values = 0.35 V; assumes output driver V OL Pull-up resistor value ( ) 15 mA [1] Nominal +10 % Nominal 310 341 197 217 143 158 97 106 range and resistor tolerance ...

Page 12

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 16

... NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 15 ...

Page 17

... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 18

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 19

... Revision history Document ID Release date PCA9306_2 20070221 • Modifications: Table 1 “Ordering – changed topside mark for type number PCA9306GM from “P06” to “P6X” – added PCA9306_1 20061020 PCA9306_2 Product data sheet Dual bidirectional I maximum peak temperature = MSL limit, damage level ...

Page 20

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 21

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Application information 11.1 Bidirectional translation ...

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