pca9624 NXP Semiconductors, pca9624 Datasheet - Page 16

• Manufacturer Part Number: pca9624
• Description: 8-bit Fm+ I2c-bus 100 Ma 40 V Led Driver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Characteristics of the I
PCA9624_1
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
8.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 8.
Fig 9.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 01 — 3 June 2009
9).
Figure
data valid
data line
stable;
10).
Figure
8-bit Fm+ I
allowed
change
of data
8).
2
C-bus 100 mA 40 V LED driver
STOP condition
mba607
PCA9624
P
© NXP B.V. 2009. All rights reserved.
mba608
16 of 34