pca9634 NXP Semiconductors, pca9634 Datasheet - Page 27

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pca9634

Manufacturer Part Number
pca9634
Description
Pca9634 8-bit Fm I2c-bus Led Driver
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
[5]
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PCA9634_4
Product data sheet
Fig 19. Definition of timing
Fig 20. I
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
SDA
SCL
Rise and fall times refer to V
2
C-bus timing diagram
P
protocol
t
SDA
SCL
BUF
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
S
t
SU;STA
t
BUF
condition
t
START
HD;STA
t
LOW
(S)
t
HD;STA
IL
f
.
and V
t
LOW
t
r
t
t
r
HD;DAT
MSB
bit 7
(A7)
IH
.
t
HIGH
Rev. 04 — 5 January 2007
t
SU;DAT
t
f
t
HIGH
1
/f
bit 6
(A6)
SCL
t
t
HD;DAT
f
t
SU;DAT
bit 7
(D1)
t
VD;DAT
Sr
(D0)
bit 8
t
SU;STA
t
t
VD;ACK
HD;STA
f
acknowledge
) for the SDA output stage is specified at
8-bit Fm+ I
(A)
t
SU;STO
IL
of the SCL signal) in order to
002aab285
t
SP
condition
t
SU;STO
STOP
PCA9634
2
(P)
© NXP B.V. 2007. All rights reserved.
C-bus LED driver
002aaa986
P
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