pca9502 NXP Semiconductors, pca9502 Datasheet - Page 12

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pca9502

Manufacturer Part Number
pca9502
Description
8-bit I/o Expander With I2c-bus/spi Interface
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PCA9502_3
Product data sheet
Fig 10. Master writes to slave
Fig 11. Master read from Slave
S
White block: host to PCA9502
Grey block: PCA9502 to host
White block: host to PCA9502
Grey block: PCA9502 to host
SLAVE ADDRESS
S
SLAVE ADDRESS
The register read cycle (see
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
Table 12.
Bit
7
6:3
2:1
0
W
Register address byte (I
Name
-
A[3:0]
-
-
A
W
REGISTER ADDRESS
Rev. 03 — 13 October 2006
A
REGISTER ADDRESS
Figure
Function
not used
internal register select
not used, set to 0
not used
2
C-bus)
11) commences in a similar manner, with the master
A
8-bit I/O expander with I
nDATA
S
A
SLAVE ADDRESS
A
nDATA
LAST DATA
A
2
002aab047
C-bus/SPI interface
R
PCA9502
© NXP B.V. 2006. All rights reserved.
P
NA
A
002aab048
P
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