pca9518a NXP Semiconductors, pca9518a Datasheet - Page 7

• Manufacturer Part Number: pca9518a
• Description: Pca9518a Expandable 5-channel I?c-bus Hub
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9518A_1
Product data sheet
In order to illustrate what would be seen in a typical application, refer to
bus master in
the waveform shown in
the small foot preceding each clock LOW-to-HIGH transition and proceeding each data
LOW-to-HIGH transition for the master. The foot height is the difference between the LOW
level driven by the master and the higher voltage LOW level driven by the PCA9518A
repeater. Its width corresponds to an effective clock stretching coming from the
PCA9518A that delays the rising edge of the clock. That same magnitude of delay is seen
on the rising edge of the data. The foot on the rising edge of the data is extended through
the 9
master. The clock of the slave looks normal except the V
by the PCA9518A. The SDA at the slave has a particularly interesting shape during the 9
clock cycle where the slave pulls the line below the value driven by the PCA9518A during
the acknowledge and then returns to the PCA9518A level creating a foot before it
completes the LOW-to-HIGH transition. SDA lines other than the one with the master and
the one with the slave have a uniform LOW level driven by the PCA9518A repeater.
The other four waveforms are the expansion bus signals and are included primarily for
timing reference points. All timing on the expansion bus is with respect to 0.5V
EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below
0.3V
EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below
0.3V
below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held
down by the PCA9518A to 0.5 V until after the delay of the circuit which determines that
it was the last to rise, then it is allowed to rise above the 0.5 V level driven by the
PCA9518A. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the
EXPSDA1 returns to HIGH after the EXPSDA2 is HIGH and either the bus 0 SDA rise time
is 1 s or, when the bus 0 SDA reaches 0.7V
EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The
same description applies for the EXPSCL1, EXPSCL2, and SCL pins.
0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held
DD
DD
th
clock pulse as the PCA9518A repeats the acknowledge from the slave to the
. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is 0.4 V.
. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is
Figure 5
were to write to the slave through the PCA9518A, we would see
Figure
Rev. 01 — 6 June 2007
6. This looks like a normal I
DD
, whichever occurs first. After both
Expandable 5-channel I
OL
2
C-bus transmission except for
is the 0.5 V level generated
PCA9518A
© NXP B.V. 2007. All rights reserved.
Figure
2
DD
C-bus hub
6. If the
.
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th