pca9535d NXP Semiconductors, pca9535d Datasheet - Page 9

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pca9535d

Manufacturer Part Number
pca9535d
Description
16-bit I2c And Smbus, Low Power I/o Port With Interrupt
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PCA9535_PCA9535C_3
Product data sheet
6.5.1 Writing to the port registers
6.5 Bus transactions
Data is transmitted to the PCA9535/PCA9535C by sending the device address and
setting the least significant bit to a logic 0 (see
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9535/PCA9535C are configured to operate as four
register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and
Configuration Ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see
sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
Fig 7. Simplified schematic of I/Os
configuration
write polarity
shift register
shift register
shift register
write pulse
read pulse
(1) PCA9535C I/Os are open-drain only. The portion of the PCA9535 schematic marked inside the
data from
data from
data from
pulse
pulse
At power-on reset, all registers return to default values.
dotted line box is not in PCA9535C.
write
configuration
register
D
CK
FF
Q
Q
Rev. 03 — 4 October 2007
16-bit I
output port
register
D
CK
2
Figure 8
FF
C-bus and SMBus, low power I/O port with interrupt
Q
and
PCA9535; PCA9535C
input port
register
polarity inversion
register
D
CK
D
CK
Figure
Figure 6 “PCA9535; PCA9535C device
FF
FF
Q
Q
9). For example, if the first byte is
(1)
Q1
Q2
© NXP B.V. 2007. All rights reserved.
output port
register data
V
I/O pin
V
input port
register data
to INT
polarity
inversion
register data
DD
SS
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