lm12l458civf National Semiconductor Corporation, lm12l458civf Datasheet - Page 23

• Manufacturer Part Number: lm12l458civf
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

2.0 Internal User-Programmable
Registers
full calibration mode because eight samples of the offset
voltage are taken, averaged, and used to create a correction
value.
Bit 7 is used to program the SYNC pin (29) to operate as
either an input or an output. The SYNC pin becomes an
output when Bit 7 is a “1” and an input when Bit 7 is a “0”.
With SYNC programmed as an input, the rising edge of any
logic signal applied to pin 29 will start a conversion or
“watchdog” comparison. Programmed as an output, the logic
level at pin 29 will go high at the start of a conversion or
“watchdog” comparison and remain high until either have
finished. See Instruction RAM “00”, Bit 8.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A “00” selects Instruction RAM section
one, “01” selects section two, and “10” selects section three.
Bit 10 activates the Test mode that is used only during
production testing. Leave this bit reset to “0”.
Bit 11 is the Diagnostic bit and is available only in the
LM12L458. It can be activated by setting it to a “1” (the Test
bit must be reset to a “0”). The Diagnostic mode, along with
a correctly chosen instruction, allows verification that the
LM12L458’s ADC is performing correctly. When activated,
the inverting and non-inverting inputs are connected as
shown in Table 1. As an example, an instruction with “001”
for both V
typically results in a full-scale output.
2.3 INTERRUPTS
The LM12L458 has eight possible interrupts, all with the
same priority. Any of these interrupts will cause a hardware
interrupt to appear on the INT pin (31) if they are not masked
(by the Interrupt Enable register). The Interrupt Status reg-
ister is then read to determine which of the eight interrupts
has been issued.
The Interrupt Status register, 1010 (A4–A1, BW = 0) or
1010x (A4–A0, BW = 1) must be cleared by reading it after
writing to the Interrupt Enable register. This removes any
spurious interrupts on the INT pin generated during an Inter-
rupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12L458 are operating in the “watchdog” comparison
Selection
Channel
Data
000
001
010
100
101
011
110
111
Channel Configuration Showing Normal
TABLE 1. LM12L458 Input Multiplexer
IN+
and V
Mode and Diagnostic Mode
V
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
(Continued)
Normal Mode
IN+
IN−
while using the Diagnostic mode
GND
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN−
Diagnostic Mode
V
V
IN2
IN3
IN4
IN5
IN6
IN7
REF+
IN+
V
V
IN2
IN3
IN4
IN5
IN6
IN7
REF−
IN−
23
mode. Two sequential comparisons are made when the
LM12L458 are executing a “watchdog” instruction. Depend-
ing on the logic state of Bit 9 in the Instruction RAM’s second
and third sections, an interrupt will be generated either when
the input signal’s magnitude is greater than or less than the
programmable limits. (See the Instruction RAM, Bit 9 de-
scription.) The Limit Status register will indicate which pro-
grammed limit, #1 or #2 and which instruction was executing
when the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10. This flag appears before the instruc-
tion’s execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 0001 to 1111, representing 1 to 31 con-
versions stored in the FIFO. A user-programmed value of
0000 has no meaning. See Section 3.0 for more FIFO infor-
mation.
The completion of the short, single-sampled auto-zero cali-
bration generates Interrupt 3.
The completion of a full auto-zero and linearity self-
calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an
instruction that has its Pause bit (Bit 1 in Instruction RAM
“00”) set to “1”.
Interrupt 7 is issued after a short delay (10 ms typ) while the
LM12L458 returns from Standby mode to active operation
using the Configuration register’s Bit 4. This short delay
allows the internal analog circuitry to settle sufficiently, en-
suring accurate conversion results.
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by
placing a “1” in the appropriate bit location. Any of the
internal interrupt-producing operations will set their corre-
sponding bits to “1” in the Interrupt Status register regardless
of the state of the associated bit in the Interrupt Enable
register. See Section 2.3 for more information about each of
the eight internal interrupts.
Bit 0 enables an external interrupt when an internal “watch-
dog” comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt
Enable register.
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 is a “Don’t Care”.
Bit 7 enables an external interrupt when the LM12L458
return from power-down to active mode.
Bits 8–10 form the storage location of the user-
programmable value against which the Sequencer’s address
is compared. When the Sequencer reaches an address that
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