uda1384 NXP Semiconductors, uda1384 Datasheet
uda1384
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uda1384 Summary of contents
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... The device also supports a combination of the MSB-justified output format and the LSB-justified input format. The UDA1384 has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus ...
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... Multichannel audio coder-decoder 2 S-bus, MSB-justified, LSB-justified and two stereo) with programmable gain amplifiers stereo all voltages referenced to ground L Min Typ 2.7 3.3 2.7 3.3 2.7 3 kHz DAC = 48 kHz © Koninklijke Philips Electronics N.V. 2005. All rights reserved. UDA1384 Max Unit 3.6 V 3 ...
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... A-weighted signal-to-noise ratio code = 0; A-weighted channel separation Ordering information Package Name Description QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder = all voltages referenced to ground L Min Typ Max - ...
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... INTERFACE 30 VOLUME, MUTE, DE-EMPHASIS INTERPOLATION FILTER UDA1384 NOISE SHAPER 32 DAC DAC DAC DDA(DA) SSA(DA) Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder SSA(AD) ADCP ADCN ref ADC 1R PGA ADC 2R PGA TEST CLOCK 2 I ...
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... DO ADC 2 data output 13 DO ADC 1 data output 14 DIS ADC bit clock input 15 DI ADC word select input Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder 33 VOUT2P 32 VOUT1N 31 VOUT1P 30 I2C_L3 29 V DDD 28 V SSD ...
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... Pin types Description analog ground analog input and output analog supply digital ground digital input digital input with internal pull-down resistor digital input and output Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder , 384f , 512f or 768f C-bus DAC mute control input ...
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... Functional description 8.1 System clock The UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock. The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes) ...
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... Philips Semiconductors 8.2 Audio analog-to-digital converter (audio ADC) The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended ADCs with programmable gain stage (from with 3 dB steps), controlled via the microcontroller interface. Using the PGA feature possible to accept an input signal of 900 mV (RMS ...
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... This noise shaping technique enables high signal-to-noise ratios to be achieved. 8.8 Digital mixer The UDA1384 has 6 digital mixers inside the interpolator (see can be mixed with the I selected by the bits MIX[1:0]. 9397 750 14366 Product data sheet Decimation fi ...
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... Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC. 8.10 Power-on reset The UDA1384 has an internal power-on reset circuit which initializes the device (see Figure 5). All the digital sound processing features and the system controlling features are ...
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... DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz The formats are illustrated in 9397 750 14366 Product data sheet V DDA(AD) (V) RESET CIRCUIT mgu585 Fig 6. Power-on reset timing Figure 7 and Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder 3.3 V DDD ( ref (V) 1.65 1.25 ...
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LEFT BCK DATA MSB S-BUS FORMAT WS LEFT BCK DATA MSB B2 LSB MSB-JUSTIFIED FORMAT WS LEFT BCK DATA WS LEFT 20 19 BCK DATA MSB B2 WS ...
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BCK DATA MSB LSB MSB CH1 CH3 BCK DATA MSB LSB MSB CH1 CH3 BCK DATA MSB LSB MSB CH1 (1) Format 1. (2) ...
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... DATA MSB B2 Fig 9. Voice digital interface formats 8.13 DSD mode The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1384 in the DSD mode is shown in DATADA2 left channel 2.8224 MHz ...
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... L3-bus interface 9.1 General The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The exchange of data and control information between the microcontroller and the UDA1384 is LSB first and is accomplished through a serial hardware L3-bus interface comprising the following pins: • ...
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... The device address consists of one byte with: • Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table • Address bits representing a 6-bit device address. The address of the UDA1384 is 01 0100 (bits 2 to 7). Table 13: DOM 9.3 Register addressing ...
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L3CLOCK L3MODE device address L3DATA 0 1 DOM bits Fig 11. Data write mode L3CLOCK L3MODE device address register address L3DATA DOM bits read prepare read Fig 12. Data read mode register address data byte 1 0 ...
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... A6 transfer address data data D15 D14 transfer byte 1 data data D7 D6 transfer byte 2 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Figure 11. For writing data to a 14): Bit 2 Bit 3 Bit 4 Bit D13 D12 D11 ...
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... The UDA1384 has an I with the I accessible via pin MCMODE with signal QMUTE. The exchange of data and control information between the microcontroller and the UDA1384 is accomplished through a serial hardware interface comprising the following pins as shown in • MCCLK: clock line with signal SCL • ...
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... SCL data line stable; data valid 2 C-bus Byte transfer START condition Figure 15). At the acknowledge bit the data line is released by the Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder change of data allowed mbc621 Table 16 STOP condition 2 C-bus © ...
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... Before any data is transmitted on the I addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1384 acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1384 device address is shown in ...
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... Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1384 repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1384. 8. Finally, the UDA1384 frees the I condition (P). ...
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... Then the microcontroller generates the device address ‘0011 000’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1384. 8. The UDA1384 sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master). ...
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... DAC mixing channel 4 DAC mixing channel 5 DAC mixing channel 6 audio ADC input amplifier gain voice ADC input amplifier gain supplemental settings 1 supplemental settings 2 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Register mapping [1] Table 21: UDA1384 register mapping Add Function D15 D14 D13 System settings [2] 00h system RST VFS1 VFS0 - 0 0 01h audio ADC and DAC DC PAB PAA subsystem 02h voice ADC system - - - Status (read out only) 0Fh status outputs - - - ...
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... Table 21: UDA1384 register mapping …continued Add Function D15 D14 D13 19h DAC mixing - - - channel 1Ah DAC mixing ICS1 ICS0 - channel 1Bh DAC mixing - - - channel 1Ch DAC mixing ICS1 ICS0 - channel 1Dh DAC mixing ...
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... ADC clock enable. Bit ACE enables the audio ADC clock 1 = clock enabled (default clock disabled ADP ADC power control. Bit ADP is to reduce the power consumption of the audio ADC state is power- state is power-off (default) Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder VCE VAP DSD 1 ...
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... DAC mode or 768f ) SYSCLK (128f , 256f 512f or 768f ) 768f ) WSDA ( SYSCLK (128f , 256f s 512f or 768f ) s s WSDA ( © Koninklijke Philips Electronics N.V. 2005. All rights reserved. UDA1384 Remark default Remark , 384f , default 384f , ...
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... Data interface selection. A 2-bit value to select the data interface connection. Default 00. See DIF[2:0] DAC input data interface format. A 3-bit value to select the used data 2 format to the I S-bus DAC input interface. Default 000. See Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder MTB MTA AIF2 ...
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... ADC 1 = WSV-in mode (default WSV-out mode VH[1:0] Voice ADC high-pass filter setting. A 2-bit value to enable the high-pass filter of the voice ADC. Default 01. See Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Function 2 I S-bus format (default) LSB-justified format, 16 bits LSB-justified format, 20 bits LSB-justifi ...
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... Voice ADC high-pass filter setting bits VH0 Function 0 high-pass filter off 0.00008f 0.0125f 0.025f c s Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder …continued (default) © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... DS0 DAC channel 1 and 2 status. Bit DS0 indicates the hard mute status of DAC channel 1 and power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder ...
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... Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder MC4 MC3 MC2 read and write CS4 CS3 CS2 read and write Table 41. Table 42. Table 41. no channel ready (default) channel 1 selected ...
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... VC[7:0] Interpolator volume control. An 8-bit value to program the volume attenuation of each channel. The range is from steps of 0.25 dB, from steps and Default 0000 0000. See Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder DE1 DE0 ...
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... Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Function no de-emphasis (default) de-emphasis of 32 kHz de-emphasis of 44.1 kHz de-emphasis of 48 kHz de-emphasis of 96 kHz not used not used not used VC2 VC1 VC0 ...
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... DAC mixing channel 1, 3 and 5 registers (address 18h, 1Ah and 1Ch) bit allocation ICS1 ICS0 - VC7 VC6 VC5 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder DE1 DE0 read and write VC4 VC3 VC2 ...
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... Default 0000. See Audio ADC input amplifier gain bits IA2 IA1 IB2 IB1 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder read and write VC4 VC3 VC2 0 ...
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... Voice ADC input amplifier gain bits IV3 IV2 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder …continued IA0 Gain (dB) IB0 0 +18 1 + read and write IV4 IV3 IV2 ...
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... DAC dither control. A 3-bit value to control the dithering of the SDAC. Default 000. See - default 00 VMTP Voice mute period control. Bit VMPT selects the voice ADC mute period at power-up mute for 1024 samples (1024 mute for 2048 samples (2048/f Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder ...
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... HBM voltage MM Thermal characteristics Parameter thermal resistance from junction to ambient Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder …continued Function DC dither (mid level); default reserved reserved reserved DC dither (low level) DC plus AC dither (low level) DC dither (high level) ...
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... ADC DAC kHz VOICE kHz; ADC DAC kHz VOICE audio and voice ADCs power-down DAC power-down with respect to V SSA(AD) Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder ); unless otherwise SS Min Typ Max 2.7 3.3 3.6 2.7 3.3 3.6 2.7 3.3 3 ...
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... Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder ); unless otherwise SS Min Typ Max - ...
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... A-weighted code = 0; A-weighted at 0 dBFS digital input at 0 dBFS at 20 dBFS at 60 dBFS; A-weighted code = 0; A-weighted Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder = 48 kHz; all voltages s Min Typ Max Unit - ...
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... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys Figure 17) Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder = 48 kHz; all voltages s Min Typ - 1.0 - < 0 105 - 110 Min Typ Max [ 780 ...
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... L3DATA delay time for read d(L3)R data 9397 750 14366 Product data sheet = +85 C; typical timing specified at sampling frequency amb Conditions and Figure 19) Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Min Typ Max - - [ ...
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... To be suppressed by the input filter. t CWH Fig 16. System clock timing 9397 750 14366 Product data sheet = +85 C; typical timing specified at sampling frequency amb Conditions 20) t CWL T sys Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Min Typ Max 400 1 0.6 ...
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... Product data sheet t t h(WS su(WS) t BCKL t d(DATAO-WS) t h(L3)A t CLK(L3 CLK(L3)H su(L3)A t su(L3)DA BIT 0 Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder t d(DATAO-BCK) t h(DATAO) t su(DATAI) t su(L3)A t h(L3)A T cy(CLK)(L3) t h(L3)DA BIT 7 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. t h(DATAI) mgs756 mgl723 ...
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... Product data sheet t CLK(L3)L t CLK(L3)H t su(L3)DA t h(L3)DA BIT 0 t h(L3 SU;DAT t SU;STA t HIGH Sr Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder t stp(L3 h(L3)D cy(CLK)L3 BIT dis(L3)R su(L3)R mgu015 HD;STA SU;STO P © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Rev. 02 — 17 January 2005 Multichannel audio coder-decoder detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. UDA1384 SOT307 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 97-08-01 03-02- ...
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... If wave soldering is used the following conditions must be observed for optimal results: 9397 750 14366 Product data sheet 2 called small/thin packages. Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... Hot bar soldering or manual soldering is suitable for PMFP packages. 9397 750 14366 Product data sheet 10 C measured in the atmosphere of the reflow oven. The package Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Added values for I characteristics”: Removed PSRR specification and (THD+N)/S at Preliminary specification - Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder Doc. number Supersedes 9397 750 14366 UDA1384_1 DDD(pd) DDD(pd) 9397 750 12043 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Rev. 02 — 17 January 2005 UDA1384 Multichannel audio coder-decoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands UDA1384 Multichannel audio coder-decoder Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register mapping . . . . . . . . . . . . . . . . . . . . . . 23 Address mapping . . . . . . . . . . . . . . . . . . . . . . 23 Register mapping ...