uda1342ts-n1 NXP Semiconductors, uda1342ts-n1 Datasheet - Page 21
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uda1342ts-n1
Manufacturer Part Number
uda1342ts-n1
Description
Audio Codec
Manufacturer
NXP Semiconductors
Datasheet
1.UDA1342TS-N1.pdf
(44 pages)
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9
The addresses of the control registers with default values at Power-on reset are shown in Table 19. Functions of the registers are shown in
Tables 20 to 45.
Table 19 Register map
00H
01H
02H to 0FH reserved
10H
11H
12H
13H to 1FH reserved
20H
21H
22H to 2FH reserved
30H
31H to FFH reserved
ADDRESS
REGISTER MAPPING
system
sub system
DAC features
DAC master volume
DAC mixer volume
ADC input and mixer
gain channel 1
ADC input and mixer
gain channel 2
evaluation
FUNCTION
RST
D15
VB7
VL7
M1
0
0
0
0
0
0
0
0
D14
VB6
VL6
QS
M0
0
0
0
0
0
0
0
0
0
MDC
D13
BB3
VL5
VB5
0
0
0
0
0
0
0
0
0
BB2
VB4
D12
VL4
DC
1
0
0
0
0
0
0
0
0
AM2 AM1 AM0 PAD
BB1
VB3
D11
VL3
IA3
IB3
1
0
0
0
0
0
0
BB0
VB2
D10
VL2
IA2
IB2
0
0
0
0
0
0
0
TR1
VB1
VL1
IA1
IB1
D9
1
0
0
0
0
0
0
TR0 SDS MTB MTA
VB0
VL0
IA0
IB0
D8
0
0
0
0
0
0
0
OS1 OS0 MPS MIX
VR7
MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
VA7
D7
0
0
0
0
0
0
0
0
0
SC1
VR6
VA6
D6
0
0
0
0
0
0
0
0
SC0
VR5
VA5
D5
0
0
0
0
0
0
0
0
VR4
VA4
IF2
MT
D4
0
0
0
0
0
0
0
0
SD1
VR3
VA3
QM
IF1
D3
0
0
0
0
0
0
0
0
SD0 MP1 MP0
DE2
VR2
VA2
IF0
D2
0
0
0
0
0
0
0
0
DE1 DE0
VR1 VR0
VA1
DP
D1
1
0
0
0
0
0
0
0
PDA
VA0
D0
0
0
0
0
0
0
0
0
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