clc5632 National Semiconductor Corporation, clc5632 Datasheet - Page 12

• Manufacturer Part Number: clc5632
• Description: Dual, High Output, Programmable Gain Buffer
• Manufacturer: National Semiconductor Corporation

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Application Division
The denominator of Equation 1 is approximately equal to 1 at
low frequencies. Near the −3dB corner frequency, the inter-
action between R
mance. The value of the feedback resistor has a large affect
on the circuits performance. Increasing R
affects:
CLC5632 Design Information
Closed Loop Gain Selection
The CLC5632 is a current feedback op amp with R
1k
gains without using any external gain or feedback resistors.
Implement gains of +2, +1, and −1V/V by connecting pins 2
and 3 (or 5 and 6) as described in the chart below.
The gain accuracy of the CLC5632 is excellent and stable
over temperature change. The internal gain setting resistors,
R
tion of
Although their absolute values change with processing and
temperature, their ratio (R
nal resistor is used in series with R
temperature will suffer.
Single Supply Operation (V
The specifications given in the +5V Electrical Characteris-
tics table for single supply operation are measured with a
common mode voltage (V
around which the inputs are applied and the output voltages
are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5632 is typically +0.8V to
+4.2V. The typical output range with R
+4.0V.
For single supply DC coupled operation, keep input signal
levels above 0.8V DC, AC coupling and level shifting the
signal are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in the
following 2 sections.
• Z(j )/R
• Decreases loop gain
• Decreases bandwidth
• Reduces gain peaking
• Lowers pulse response overshoot
• Affects frequency response phase linearity
Gain A
−1V/V
+1V/V
+2V/V
f
and R
on chip (in the package). Select from three closed loop
±
V
20% and a temperature coefficient of - 2000ppm/˚C.
g
f
are diffused silicon resistors with a process varia-
is the loop gain
Input Connections
Non-Inverting (pins 3, 5)
ground
input signal
input signal
f
and Z(j ) dominates the circuit perfor-
f
/R
CM
g
) remains constant. If an exter-
CC
) of 2.5V. V
= +5V, V
(Continued)
g
, gain accuracy over
L
Inverting (pins 2, 6)
input signal
NC (open)
ground
= 100
f
EE
CM
has the following
= GND)
is the voltage
is +1.0V to
f
= R
g
=
12
DC Coupled Single Supply Operation
Figure 1 , Figure 2 , and Figure 3 on the following page, show
the recommended configurations for input signals that re-
main above 0.8V DC.
V
V
FIGURE 1. DC Coupled, A
FIGURE 2. DC Coupled, A
FIGURE 3. DC Coupled, A
o
o
R
R
L
V
L
V
Note: R
consumption and maximum output swing.
Channel 2 not shown.
cm
Note: R
consumption and maximum output swing.
Channel 2 not shown.
cm
V
V
t
in
and R
t
, R
in
R
L
V
V
R
and R
t
L
cm
V
cm
t
are tied to V
cm
g
are tied to V
3
2
4
1
3
2
4
1
cm
for minimum power
1k
CLC5632
cm
1k
CLC5632
1k
for minimum power
1k
+
V
1k
-
V
V
+
-
1k
-
+
+
-
= −1V/V Configuration
= +1V/V Configuration
= +2V/V Configuration
1k
1k
8
7
6
5
8
7
6
5
V
CC
V
CC
6.8 F
0.1 F
+
DS015003-40
6.8 F
0.1 F
+
DS015003-39
DS015003-41