hi3-7153j-5 Intersil Corporation, hi3-7153j-5 Datasheet - Page 15

• Manufacturer Part Number: hi3-7153j-5
• Description: 8-channel, 10-bit High Speed Sampling Converter
• Manufacturer: Intersil Corporation

Dynamic Performance
Fast Fourier Transform (FFT) techniques are used to evalu-
ate the dynamic performance for one channel of the A/D
system. A low distortion sine wave is applied to the input of
the A/D converter. The input is sampled by the A/D and its
output stored in RAM. The data is then transformed into the
frequency domain with a 4096 point FFT and analyzed to
evaluate the converters dynamic performance such as SNR
and THD. See typical performance characteristics.
Signal-To-Noise Ratio
The signal to noise ratio (SNR) is the measured rms signal to
rms sum of noise at a specified input and sampling
frequency. The noise is the rms sum of all except the funda-
mental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N +
1.76)dB. For an ideal 10 bit converter the SNR is 62dB.
Differential and integral linearity errors will degrade SNR.
Signal-To-Noise + Distortion Ratio
SINAD is the measured rms signal to rms sum of noise plus
harmonic power and is expressed by the following.
Effective Number of Bits
The effective number of bits (ENOB) is derived from the
SINAD data;
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
the fundamental RMS signal for a specified input and
sampling frequency.
Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the RMS amplitude of the
next largest spur or spectral component. It is usually deter-
mined by the largest harmonic. However, if the harmonics
are buried in the noise floor it is the largest peak.
Clock
The clock input is TTL compatible. The converter will func-
tion with clock inputs between 10kHz and 800kHz.
THD
SINAD
SFDR
=
10
=
log
SNR
10
=
Total Harmonic Power (2nd - 6th harmonics)
------------------------------------------------------------------------------------------------------------------
log
10
ENOB
=
------------------------------------------------------------------------------------------------------- -
Noise + Harmonic Power (2nd thru 6th)
log
10
----------------------------------------------------------------------------------
Highest Spurious Signal Power
log
Sinewave Signal Power
=
Sinewave Signal Power
Sinewave Signal Power
Sinewave Signal Power
------------------------------------------------------- -
SINAD 1.76
----------------------------------- -
Total Noise Power
6.02
–
HI-7153
15
Microprocessor Interface
The HI-7153 can be interfaced to microprocessors through
the use of standard Write, Read, Chip Select, and HBE con-
trol pins. The digital outputs are two’s complement coded,
three-state gated, and byte organized for bus interface with
8 and 16 bit systems. The digital outputs (D0 - D9, OVR)
may be accessed under control of BUS, byte enable input
HBE, chip select, and read inputs for a simple parallel bus
interface. The microprocessor can read the current data in
the output latches in typically 60ns/byte (t
pin (OVR) together with the MSB (D9) pin set to either a
logic 0 or 1 will indicate a positive or negative over-range
condition respectively. All digital output buffers are capable
of driving one TTL load. The multiplexer can be interfaced to
either multiplexed or separate address and data bus sys-
tems.
The HI-7153 can be interfaced to a microprocessor using one
of three modes: slow memory, fast memory, or DMA mode.
Slow Memory Mode
In slow memory mode, the conversion will be initiated by the
microprocessor by selecting the chip (CS) and pulsing WR
low. This mode is selected by hardwiring the SMODE pin to
V+. Note that the converter will change to the DMA interface
mode if the WR to RD active timing is less than 100ns. The
end-of-conversion (EOC) output signals an interrupt for the
microprocessor to jump to a read subroutine at the end of
conversion. When the 8 bit bus operation is selected, high
and low byte data may be accessed in either order. An I/O
truth table is presented in Table 3 for the slow memory mode
of operation.
Fast Memory Mode
The fast memory mode of operation is selected by tying the
SMODE and WR pins to DG. In this mode, the chip performs
continuous conversions and only CS and RD are required to
read the data. Whenever the SMODE pin is low, WR is inde-
pendent of CS in starting a conversion cycle. During the first
conversion cycle, HOLD follows WR going low. HOLD will be
one clock period wide for subsequent conversion cycles.
Data can be read a byte at a time or all 11 bits at once.
When the 8 bit bus operation is selected, high and low byte
data may be accessed in either order. EOC is continuously
low in this mode of operation. The conversion data can be
read after HOLD has gone low. An I/O truth table is
presented in Table 4 for the fast memory mode of operation.
DMA Mode
This is a hardwired mode where the HI-7153 continuously
converts. The user implements hardware to store the results
in memory, bypassing the microprocessor. This mode is
recognized by the chip when SMODE is connected to V+
and CS, RD, WR are connected to DG. When 8 bit bus
operation is selected, high and low byte data may be
accessed in either order. EOC is continuously low in this
mode. The conversion data can be read approximately
300ns after HOLD has gone low. An I/O truth table is
RD
). An over-range