kad5612p Kenet Inc., kad5612p Datasheet - Page 22

• Manufacturer Part Number: kad5612p
• Description: Dual 12-bit, 250/210/170/125msps A/d Converter
• Manufacturer: Kenet Inc.

Address 0x71: phase_slip
When using the clock divider, it’s not possible to de-
termine the synchronization of the incoming and di-
vided clock phases. This is particularly important
when multiple ADCs are used in a time-interleaved
system. The phase slip feature allows the rising edge
of the divided clock to be advanced by one input
clock cycle, as shown in Figures 39 and 40. This regis-
ter is self-clearing.
Address 0x72: clock_divide
The KAD5612P has a selectable clock divider that
can be set to divide by four, two or one (no division).
By default, the tri-level CLKDIV pin selects the divisor
(refer to Clock Input section). This functionality can
be overridden and controlled through the SPI, as
shown in Table 12. This register is not changed by a
Soft Reset.
Figure 40. Phase Slip: CLK÷4 Mode, f
Figure 39. Phase Slip: CLK÷2 Mode, f
KAD5612P
CLOCK
CLOCK
=1000MHz
=500MHz
Address 0x73: output_mode_A
The output_mode_A register controls the physical
output format of the data, as well as the logical cod-
ing. The KAD5612P can present output data in two
physical formats: LVDS or LVCMOS. Additionally, the
drive strength in LVDS mode can be set high (3mA) or
low (2mA). By default, the tri-level OUTMODE pin se-
lects the mode and drive level (refer to Digital Out-
puts section). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default,
the tri-level OUTFMT pin selects the data format (refer
to Data Format section). This functionality can be
overridden and controlled through the SPI, as shown
in Table 14.
This register is not changed by a Soft Reset.
Address 0x74: output_mode_B
Address 0x75: config_status
Bit 6
DLL Range
This bit sets the DLL operating range to fast
(default) or slow.
Table 12. Clock Divider Selection
Table 14. Output Format Control
Table 13. Output Mode Control
Value
Value
Value
000
001
010
100
000
001
010
100
000
001
010
100
Two’s Complement
Output Format
Clock Divider
Offset Binary
Divide by 1
Divide by 2
Divide by 4
Gray Code
Pin Control
Pin Control
Pin Control
LVDS 2mA
LVDS 3mA
0x72[2:0]
0x93[7:5]
0x93[2:0]
LVCMOS
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