kad5512hp Kenet Inc., kad5512hp Datasheet - Page 19

• Manufacturer Part Number: kad5512hp
• Description: High Performance 12-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

An external resistor creates the bias for the LVDS driv-
ers. A 10kΩ, 1% resistor must be connected from the
RLVDS pin to OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output
code reaches positive full-scale (e.g. 0xFFF in offset
binary mode). The output code does not wrap
around during an over-range condition. The OR bit is
updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5512HP is primarily
dependent on the sample rate and the output
modes: LVDS vs. CMOS and DDR vs. SDR. There is a
static bias in the analog supply, while the remaining
power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a
lesser degree in LVDS mode, but is more strongly re-
lated to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save
power during times when operation of the ADC is not
required. Two power saving modes are available:
Nap, and Sleep. Nap mode reduces power dissipa-
tion to less than 134mW and recovers to normal op-
eration in approximately 1µs. Sleep mode reduces
power dissipation to less than 14mW but requires 1ms
to recover.
All digital outputs (Data, CLKOUT and OR) are placed
in a high impedance state during Nap or Sleep. The
input clock should remain running and at a fixed fre-
quency during Nap or Sleep. Recovery time from
Nap mode will increase if the clock is stopped, since
the internal DLL can take up to 52µs to regain lock at
250MSPS.
By default after the device is powered on, the opera-
tional state is controlled by the NAPSLP pin as shown
in Table 3.
The power down mode can also be controlled
through the SPI port, which overrides the NAPSLP pin
KAD5512HP
Table 3. NAPSLP Pin Settings
NAPSLP Pin
AVDD
AVSS
Float
Normal
Mode
Sleep
Nap
setting. Details on this are contained in the Serial Pe-
ripheral Interface section. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin.
Data Format
Output data can be presented in three formats:
two’s complement, Gray code and offset binary. The
data format is selected via the OUTFMT pin as shown
in Table 4.
The data format can also be controlled through the
SPI port, which overrides the OUTFMT pin setting. De-
tails on this are contained in the Serial Peripheral In-
terface section.
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most posi-
tive input to 0xFFF (all ones). Two’s complement cod-
ing simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged.
The remaining bits are computed as the XOR of the
current bit position and the next most significant bit.
Figure 33 shows this operation.
Converting back to offset binary from Gray code
must be done recursively, using the result of each bit
for the next lower bit as shown in Figure 34.
Figure 33. Binary to Gray Code Conversion
OUTFMT Pin
Table 4. OUTFMT Pin Settings
AVDD
AVSS
Float
Two’s Complement
Offset Binary
Gray Code
Mode
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