tda8705t NXP Semiconductors, tda8705t Datasheet - Page 8

• Manufacturer Part Number: tda8705t
• Description: 6-bit High-speed Dual Analog-to-digital Converter Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
2. Analog input voltages producing code 00 up to and including 3F:
3. Full-scale sine wave (f
4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both
5. The 0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
8. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two
9. Output data acquisition: the output data is available after the maximum delay time of t
1996 Jan 12
SYMBOL
B
BER
Timing; f
t
t
t
ds
h
d
IT ERROR RATE
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
must not be less than 1 ns.
a) V
b) V
ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE
(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.
full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.
input (square-wave signal) in order to sample the signal and obtain correct output data.
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
the reference voltage BOTTOM (V
produces data outputs equal to 3F at T
osB
osT
clk
(voltage offset TOP) is the difference between V
bit error rate
sampling delay time
output hold time
output delay time
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
= 40 MHz; C
L
i
PARAMETER
= 10 MHz; f
= 15 pF; note 9; see Fig.3
clk
= 40 MHz).
RB
) at T
amb
amb
= 25 C.
= 25 C.
f
f
V
clk
i
I
= 10 MHz;
8
= 16 LSB at code 32
= 40 MHz;
RT
CONDITIONS
(reference voltage TOP) and the analog input which
6.02 + 1.76 dB.
5
MIN.
d
.
10
TYP.
13
Product specification
2
14
TDA8705
MAX.
times/
samples
ns
ns
ns
UNIT