tda8757hl NXP Semiconductors, tda8757hl Datasheet - Page 21

• Manufacturer Part Number: tda8757hl
• Description: Triple 8-bit Adc 170 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09457
Preliminary data
9.1.8 DEMUX register
9.1.9 Power-down mode
9.2 I
Table 11: Phase registers bits
The default programmed value is as follows:
The default programming is:
Table 12: Register format
The address of the circuit for the I
Bits ‘A1’ and ‘A0’ are fixed by the potential on pins A2 and A1. Bit ‘RW’ must always
be equal to logic 0 because it is not possible to read the data in the register. The
timing and protocol for the I
see
P4
0
0
...
1
1
2
•
•
•
•
•
•
•
•
•
•
•
A6
1
C-bus protocol
No external clock: bit ‘Ckext’ is logic 0
Phase shift for CKDATA is 0 degrees.
Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1
CKREFO with positive polarity: bit ‘Ckrp’ = 0
CKDATA not reversed: bit ‘Ckdp’ = 0
CKDATA not delayed: bit ‘Ckdd’ = 0
De-multiplexed outputs: bit ‘Dmx’ = 1
Interleaved outputs: bit ‘Shift’ = 1
Odd pixels on port A: bit ‘Odda’ = 1.
When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
When the device is in Power-down mode (pin PD = HIGH), the previously
programmed register values remain unaffected.
Table 13
A5
0
and 14.
P3
0
0
...
1
1
Rev. 07 — 28 February 2002
A4
0
P2
0
0
...
1
1
2
C-bus are standard. Two sequences are available;
A3
1
2
C-bus is 1001 1XX0.
P1
0
0
...
1
1
A2
1
P0
0
1
...
0
1
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
A1
A2
Triple 8-bit ADC 170 Msps
A0
A1
TDA8757
0
...
Phase shift (deg)
11.25
337.5
348.75
RW
0
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