tda8768a NXP Semiconductors, tda8768a Datasheet - Page 11

• Manufacturer Part Number: tda8768a
• Description: 12-bit, 70 Msps Analog-to-digital Converter Adc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 6:
V
V
V
and C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
9397 750 09656
Product data
Symbol
3-state output delay times; see
t
t
t
t
dZH
dZL
dHZ
dLZ
CCA
CCO
ref
= V
D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.
The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with V
b) PECL mode 2: (DC level vary 1:1 with V
c) PECL mode 3: (DC level vary 1:1 with V
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
The ADC input range can be adjusted with an external reference connected to V
see
The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see
Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see
Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB
Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter ( 6 dB below full scale for each input signal).
d3
Output data acquisition: the output data is available after the maximum delay of t
THD
= V
= V
L
(IM3)
CCA3
= 10 pF; unless otherwise specified.
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLK or CLK input to DGND via a 100 nF capacitor.
In that case CLK pin has to be connected to the ground.
Figure
2
33
=
to V
is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
to V
Characteristics
20 log
1.75 V; V
12.
44
Parameter
enable HIGH
enable LOW
disable HIGH
disable LOW
34
, V
= 3.0 to 3.6 V; AGND and DGND shorted together; T
3
------------------------------------------------------------------------------------------------------------------------------------- -
2nd
to V
I(CM)
4
2
and V
= V
+
…continued
CCA3
3rd
41
Figure 4
to V
2
1.6V; typical values measured at V
+
40
4th
F
= 4.75 to 5.25 V; V
2
CCD
CCD
CCD
2
) CLK and CLK inputs are at differential PECL levels.
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
) CLK input is at PECL level and sampling is taken on the rising edge of the clock input
Conditions
+
5th
Rev. 02 — 03 July 2002
2
+
6th
CCD
2
= V
12-bit, 70 Msps Analog-to-Digital Converter (ADC)
37
to V
amb
CCA
38
= 40 to 85 C; V
= V
ref
d
; see
and V
Test
C
C
C
C
pin. This voltage has to be referenced to V
CCD
Figure
[1]
15
= 5 V and V
to V
Figure
Min
-
-
-
-
3.
17
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
= 4.75 to 5.25 V;
I(p-p)
6.
Typ
5.1
7.0
9.7
9.5
6.02 + 1.76 dB; see
CCO
V
TDA8768A
= 3.3 V, T
I(p-p)
Figure
= 1.9 V;
Max
9.0
11
14
13
amb
8.
= 25 C
Figure
CCA
Unit
ns
ns
ns
ns
11 of 32
;
5.