ad1833ast Analog Devices, Inc., ad1833ast Datasheet - Page 12

no-image

ad1833ast

Manufacturer Part Number
ad1833ast
Description
Multichannel 24-bit, 192 Khz, Dac
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1833AST
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Left Justified Timing
Left Justified (LJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
I
I
mitted is for the left channel and when it is for the right channel.
The L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 × f
AD1833
Right Justified Timing
Right Justified (RJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 × f
2
L/RCLK
2
SDATA
S Timing
S timing uses an L/RCLK to define when the data being trans-
INPUT
INPUT
INPUT
BCLK
L/RCLK
SDATA
L/RCLK
SDATA
INPUT
INPUT
INPUT
INPUT
INPUT
BCLK
INPUT
BCLK
LSB
MSB
MSB
–1
MSB
MSB
–2
MSB
–1
MSB
–2
LEFT CHANNEL
MSB
LSB
+2
S
LEFT CHANNEL
is used to clock in the
MSB
LSB
–1
+1
LSB
LEFT CHANNEL
+2
MSB
LSB
–2
LSB
+1
LSB
S
is used
LSB
+2
LSB
+1
LSB
MSB
data. There is a delay of one bit clock from the time the L/RCLK
signal changes state to the first bit of data on the SDINx lines.
The data is written MSB first and is valid on the rising edge of
bit clock.
low for the right channel. A bit clock running at 64 × f
to clock in the data. The first bit of data appears on the SDINx
lines at the same time the L/RCLK toggles. The data is written
MSB first and is valid on the rising edge of bit clock.
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ
mode the LSB of data is always clocked by the last bit clock
before L/RCLK transitions. The data is written MSB first and
is valid on the rising edge of bit clock.
MSB
MSB
–1
MSB
MSB
–1
–2
MSB
–2
RIGHT CHANNEL
RIGHT CHANNEL
LSB
MSB
+2
RIGHT CHANNEL
LSB
+2
LSB
MSB
+1
–1
LSB
+1
LSB
MSB
–2
LSB
LSB
+2
LSB
+1
LSB
MSB
MSB
S
MSB
–1
is used

Related parts for ad1833ast