ad1833ast Analog Devices, Inc., ad1833ast Datasheet - Page 11

• Manufacturer Part Number: ad1833ast
• Description: Multichannel 24-bit, 192 Khz, Dac
• Manufacturer: Analog Devices, Inc.

MCLK Select
The AD1833 allows the matching of available external MCLK
frequencies to the required sample rate. The oversampling rate
can be selected from 256 × f
Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of
512 × f
is used, whereas in 768 × f
first implemented, followed by a clock doubler. See Table XII.
Bit 4
0
0
1
1
Channel Zero Status
The AD1833 provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods. There is also a global zero flag that indicates all
channels contain zero data. The polarity of the active zero signal
Sampling Rate f
32
64
128
44.1
88.2
176.4
48
96
192
S
; therefore, in the case of 256 × f
Bit 3
0
1
0
1
Table XII. MCLK Settings
S
(kHz)
S
mode, a divide-by-3 block (/3) is
S
Address
15–12
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
Must be programmed to zero.
, 512 × f
Oversample Ratio
256 × f
512 × f
768 × f
Reserved
S
S
S
S
(MCLK × 2 Internally)
(MCLK × 2/3 Internally)
or 768 × f
S
Interpolator Mode
8× (Normal)
4× (Double)
2× (4 Times)
8× (Normal)
4× (Double)
2× (4 Times)
8× (Normal)
4× (Double)
2× (4 Times)
mode, a clock doubler
Table XIV. MCLK vs. Sample Rate Selection
11
0
Reserved
Table XV. Volume Control Registers
S
by writing to
10
0
Volume Control
9–0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
is programmable by writing to Control Bit 2, see Table XIII.
The six individual channel flags are best used as three stereo
zero flags by combining pairs of them through suitable logic
gates. Then, when both the left and right input are zero for 1024
clock cycles, i.e., a stereo zero input for 1024 sample periods,
the combined result of the two individual flags will go active
indicating a stereo zero.
DAC Volume Control Registers
The AD1833 has six volume control registers, one each for the
six DAC channels. Volume control is exercised by writing to the
relevant register associated with each DAC. This setting is used
to attenuate the DAC output. Full-scale setting (all 1s) is equiva-
lent to zero attenuation. See Table XV.
256 f
8.192
11.2896
12.288
Bit 2
0
1
S
Table XIII. Zero Detect
MCLK (MHz)
Channel Zero Status
Active High
Active Low
512 f
16.384
22.5792
24.576
S
AD1833
768 f
24.576
33.8688
36.864
S