adc161s626cimmx National Semiconductor Corporation, adc161s626cimmx Datasheet - Page 5

• Manufacturer Part Number: adc161s626cimmx
• Description: 16-bit, 50 To 250 Ksps, Differential Input, Micropower Adc
• Manufacturer: National Semiconductor Corporation

PWR (PD)
PSRR
AC ELECTRICAL CHARACTERISTICS
f
f
t
t
t
Symbol
SCLK
S
ACQ
CONV
AD
Symbol
ADC161S626 Timing Specifications
The following specifications apply for V
25 pF, unless otherwise noted. Maximum and minimum values apply for T
25°C.
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when the ADC161S626 is operated in a severe fault condition (e.g. when input or output pins
are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Typical values are at T
Level).
Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 9: The value of V
at 2.7V while V
Note 10: While the maximum sample rate is f
Note 11: t
t
t
t
CSS
CSH
t
t
t
t
t
t
DIS
DH
DA
CS
EN
CH
CL
t
t
r
f
DIS
CS Setup Time prior to an SCLK rising edge
CS Hold Time after an SCLK rising edge
D
D
D
Minimum CS Pulse Width
D
SCLK High Time
SCLK Low Time
D
D
Power Consumption, Power Down
Mode (CS high)
Power Supply Rejection Ratio
Maximum Clock Frequency
Maximum Sample Rate
Acquisition/Track Time
Conversion/Hold Time
Aperture Delay
OUT
OUT
OUT
OUT
OUT
OUT
is the time for D
A
is operating at 5.5V.
Hold Time after an SCLK falling edge
Access Time after an SCLK falling edge
Disable Time after the rising edge of CS (Note 11)
Enable Time after the 2nd falling edge of SCLK
Rise Time
Fall Time
IO
is independent of the value of V
Parameter
OUT
J
= 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
to change 10% while being loaded by the Timing Test Circuit.
JA
), and the ambient temperature (T
SCLK
Parameter
A
= 4.5V to 5.5V, V
/ 20, the actual sample rate may be lower than this by having the CS rate slower than f
J
max) for this device is 150°C. The maximum allowable power dissipation is dictated by T
A
. For example, V
f
(Note 8)
f
(Note 8)
See the Specification Definitions for
the test condition
(Note 10)
See the Specification Definitions
SCLK
SCLK
= 5 MHz, V
= 0 Hz, V
IO
= 2.7V to 5.5V, V
IO
Conditions
(Note 7)
A
could be operating at 5.5V while V
), and can be calculated using the formula P
5
IN
A
= 5.0V
< GND or V
A
= 5.0V
A
= T
IN
REF
> V
MIN
A
= 2.5V to 5.5V, f
), the current at that pin should be limited to 10 mA. The 50
Min
to T
20
20
20
8
8
6
MAX
A
Min
600
; the typical values are tested at T
50
1
is operating at 4.5V or V
Typ
11
18
20
20
3
3
7
7
SCLK
D
MAX = (T
Typ
−78
= 1Mz to 5MHz, and C
35
10
6
J
Max
max − T
41
30
70
SCLK
IO
could be operating
A
Max
250
/ 20.
)/θ
15
17
5
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JA
J
max, the
. The values
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
SCLK
A
Units
kSPS
MHz
L
µW
µW
dB
=
ns
ns
=