adc1112d125 NXP Semiconductors, adc1112d125 Datasheet - Page 31

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adc1112d125

Manufacturer Part Number
adc1112d125
Description
Adc1112d125 Dual 11-bit Adc; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet

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Table 20.
Default values are highlighted.
Table 21.
Default values are highlighted.
Table 22.
Default values are highlighted.
ADC1112D125
Product data sheet
Bit
7 to 2
1
0
Bit
7
6 to 4
3 to 2
1 to 0
Bit
7 to 5
4
3
2
1
0
Symbol
RESERVED[5:0]
ADCB
ADCA
Symbol
SW_RST
RESERVED[2:0]
-
OP_MODE[1:0]
Symbol
-
SE_SEL
DIFF_SE
RESERVED
CLKDIV
DCS_EN
Channel index control register (address 0003h) bit description
Reset and operating mode control register (address 0005h) bit description
Clock control register (address 0006h) bit description
All information provided in this document is subject to legal disclaimers.
Access
-
R/W
R/W
Access
R/W
-
-
R/W
Access
-
R/W
R/W
-
R/W
R/W
Rev. 2 — 3 March 2011
Value
111111
0
1
0
1
Value
0
1
000
00
00
01
10
11
Value
000
0
1
0
1
0
0
1
0
1
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Description
reserved
next SPI command for ADC B
next SPI command for ADC A
Description
reset digital section
reserved
not used
operating mode
Description
not used
single-ended clock input pin select
differential/single-ended clock input select
reserved
clock input divide by 2
duty cycle stabilizer
ADC B not selected
ADC B selected
ADC A not selected
ADC A selected
no reset
performs a reset on SPI registers
normal (Power-up)
Power-down
Sleep
normal (Power-up)
CLKM
CLKP
fully differential
single-ended
disabled
enabled
disabled
enabled
ADC1112D125
© NXP B.V. 2011. All rights reserved.
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