adc1175-50cilqx National Semiconductor Corporation, adc1175-50cilqx Datasheet - Page 15

• Manufacturer Part Number: adc1175-50cilqx
• Description: 8-bit, 50 Msps, 125 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

FIGURE 5. Driving the Reference to Force Desired Values requires driving with a low impedance source, provided by the
3.0 OUTPUT DATA TIMING
The Output Delay (t
to one half clock cycle. Because of this, the output data tran-
sition occurs very near the falling edge of the ADC clock. To
avoid clocking errors, you should use the rising edge of the
ADC clock to latch the output data of the ADC1175-50 and
not use the falling edge.
4.0 POWER SUPPLY CONSIDERATIONS
Many A/D converters draw sufficient transient current to cor-
rupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 centimeters) of the A/D power pins,
with a 0.1 µF ceramic chip capacitor placed as close as pos-
sible to the converter's power supply pins. Leadless chip
capacitors are preferred because they have low lead induc-
tance.
While a single voltage source should be used for the analog
and digital supplies of the ADC1175-50, these supply pins
should be isolated from each other to prevent any digital noise
from being coupled to the analog power pins. We recom-
mended a wide band choke, such as the JW Miller
FB20010-3B, be used between the analog and digital supply
lines, with a ceramic capacitor close to the analog supply pin.
If a resistor is used in place of the choke, a maximum of
10Ω should be used.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the A/D analog supply.
As with all high speed converters, the ADC1175-50 should be
assumed to have little a.c. power supply rejection, especially
when self biasing is used by connecting V
er.
OD
) of the ADC1175-50 can be very close
transistors. Note that pins 16 and 22 are not connected.
RT
and V
RTS
togeth-
15
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground, not even on a transient basis.
This can be a problem upon application of power to a circuit.
Be sure that the supplies to circuits driving the CLK, PD, ana-
log input and reference pins do not come up any faster than
does the voltage at the ADC1175-50 power pins.
Pins 11 and 13 are both labeled DV
point for the digital core of the ADC, where pin 13 is used only
to provide power to the ADC output drivers. As such, pin 11
may be connected to a voltage source that is less than the
+5V used for AV
age devices. Pin 11 should never exceed the pin 13 potential
by more than 0.5V.
5.0 THE ADC1175-50 CLOCK
Although the ADC1175-50 is tested and its performance is
guaranteed with a 50 MHz clock, it typically will function with
clock frequencies from 1 MHz to 55 MHz.
The clock should be one of low jitter and close to 50% duty
cycle.
6.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals is essential
to ensure accurate conversion. Separate analog and digital
ground planes that are connected beneath the ADC1175-50
may be used, but best EMI practices require a single ground
plane. However, it is important to keep analog signal lines
away from digital signal lines and away from power supply
currents. This latter requirement requires the careful separa-
tion and placement of power planes. The use of power traces
rather than one or more power planes is not recommended
as higher frequencies are not well filtered with lumped ca-
pacitances. To filter higher frequency noise components it is
DD
and DV
DD
to ease interfacing to low volt-
10089627
DD
. Pin 11 is the supply
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