adc1005s060ts NXP Semiconductors, adc1005s060ts Datasheet - Page 9

• Manufacturer Part Number: adc1005s060ts
• Description: Single 10 Bits Adc, Up To 60 Mhz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
V
measured at V
specified.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Output data acquisition: the output data is available after the maximum delay time of t
ADC1005S060_2
Product data sheet
Symbol
C
SR
3-state output delay times (f
t
t
t
t
dZH
dZL
dHZ
dLZ
CCA
L
The rise and fall times of the clock signal must not be less than 0.5 ns.
The input admittance is
Analog input voltages producing code 0 up to and including code 1023:
a) V
b) V
To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors R
a) The current flowing into the resistor ladder is
b) Since R
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
signal-to-noise ratio: S/N = ENOB
Intermodulation measured relative to either tone with analog input frequencies of 4.3 MHz and 4.5 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter.
load. These parameters are guaranteed by characterization and not by production test.
E
= 4.75 V to 5.25 V; V
G
(V
to code 1023 at T
to 1023 is
will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference V
parallel and fed with the same reference source, the matching between each of them is optimized.
=
offset
offset
RB
-------------------------------------------------------- -
) at T
Characteristics
V
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
TOP is the difference between the reference voltage on pin RT (V
1023
Parameter
load capacitance
slew rate
float to active
HIGH delay time
float to active
LOW delay time
active HIGH to
float delay time
active LOW to
float delay time
L
CCA
, R
amb
V
–
OB
V
I
= V
V
= 25 C.
i p
=
and R
0
CCD
–
R
amb
–
p
L
V
Y
OT
CCD
= 5 V; V
= 25 C
i p
i
I
+
have similar behavior with respect to process and temperature variation, the ratio
L
…continued
–
clk
---- -
R
RT
= 4.75 V to 5.25 V; AGND and DGND shorted together; T
=
1
p
i
+
.
--------------------------------------- -
R
= 60 MHz; V
Conditions
V
CCO
OB
V
100
j C
CCO
RB
6.02 + 1.76 dB.
+
and its variation with temperature and supply voltage. When several ADCs are connected in
= 3.3 V; V
i
R
R
= 2.7 V
L
L
+
R
CCO
OT
I
RB
=
Rev. 02 — 13 August 2008
= 3.3 V); see
= 1.3 V; V
V
--------------------------------------- -
R
RT
OB
V
+
RT
+
V
R
–
RB
L
V
+
RT
RB
R
Figure 5
=
= 3.7 V; C
OT
OB
0.8375
Min
-
0.2
-
-
-
-
and the full-scale input range at the converter, to cover code 0
and R
RT
) and the analog input which produces data outputs equal
OT
L
= 10 pF and T
V
as shown in
RT
d(o)
–
Typ
-
0.3
16
30
25
23
V
. NXP recommends the lowest possible output
RB
Single 10 bits ADC, up to 60 MHz
Figure
amb
amb
ADC1005S060
= 0 C to 70 C; typical values
3.
= 25 C unless otherwise
Max
10
-
20
34
30
27
--------------------------------------- -
R
OB
© NXP B.V. 2008. All rights reserved.
+
R
R
Unit
pF
V/ns
ns
ns
ns
ns
L
L
+
R
OT
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