adc10061cmw-mls National Semiconductor Corporation, adc10061cmw-mls Datasheet - Page 13

• Manufacturer Part Number: adc10061cmw-mls
• Description: 10-bit 600 Ns A/d Converter With Input Multiplexer And Sample/hold
• Manufacturer: National Semiconductor Corporation

Applications Information
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 each have two
reference inputs. These inputs, V
differential and define the zero to full-scale range of the input
signal. The reference inputs can be connected to span the
entire supply voltage range (V
ratiometric applications, or they can be connected to differ-
ent voltages (as long as they are between ground and V
when other input spans are required.
Reducing the overall V
the sensitivity of the converter (e.g., if V
= 1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used. See
the Typical Performance Curves for more information. For
this reason, reference voltages less than 2V are not recom-
mended.
In most applications, V
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated by
the reference configuration used in the ADC10061,
ADC10062, and ADC10064. V
voltage other than ground as long as the voltage source
connected to this pin is capable of sinking the converter’s
reference current (12.5 mA Max
connected to a voltage other than ground, bypass it with
multiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on
either reference input is a potential cause of conversion
errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be
bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
REF
REF−
span to less than 5V increases
will simply be connected to
REF−
REF−
@
REF+
V
= 0V, V
can be connected to a
REF
REF
and V
= 5V). If V
= 2V, then 1 LSB
REF+
(Continued)
REF−
FIGURE 4. Typical Connection
= V
, are fully
REF−
CC
) for
CC
is
)
13
3.0 THE ANALOG INPUT
The ADC10061, ADC10062, and ADC10064 sample the
analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance
approximately equal to 600Ω in series with 35 pF. Short-
duration current spikes can be observed at the analog input
during normal operation. These spikes are normal and do
not degrade the converter’s performance.
Large source impedances can slow the charging of the
sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500Ω should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier’s output should be well-behaved when
driving a switched 35 pF/600Ω load. Any ringing or voltage
shifts at the op-amp’s output during the sampling period can
result in conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V
allow the signal source to drive the analog input pin beyond
the Absolute Maximum Rating. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
damage to the IC. The sum of all the overdrive currents into
all pins must be less than the Absolute Maximum Rating for
Package Input Current. When the input signal is expected to
extend beyond this limit, an input protection scheme should
be used. A simple input protection network using diodes and
resistors is shown in Figure 4. Note the multiple bypass
capacitors on the reference and power supply pins. If V
is not grounded, it should also be bypassed to analog ground
using multiple capacitors (see 5.0 “Power Supply Consider-
ations”). AGND and DGND should be at the same potential.
V
normally left open, but optional “speedup” resistor R
be used to reduce the conversion time.
IN0
is shown with an input protection network. Pin 17 is
01102015
+
+ 50 mV. Do not
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REF−
can