adc10061cmw-mls National Semiconductor Corporation, adc10061cmw-mls Datasheet - Page 12

• Manufacturer Part Number: adc10061cmw-mls
• Description: 10-bit 600 Ns A/d Converter With Input Multiplexer And Sample/hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
SIMILAR PRODUCT DIFFERENCES
The ADC1006x, ADC1046x and ADC1066x (where "x" indi-
cates the number of multiplexer inputs) are similar devices
with different specification limits. The differences in these
device families are summarized below.
Applications Information
1.0 MODES OF OPERATION
The ADC10061, ADC10062, and ADC10064 have two basic
digital interface modes. Figure 1 and Figure 2 are timing
diagrams for the two modes. The ADC10062 and ADC10064
have input multiplexers that are controlled by the logic levels
on pins S
showing how the input channels are assigned.
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 250 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S/H goes high, the result of the coarse conver-
sion is latched and the “fine” conversion begins. After 600 ns
(typical), INT goes low, indicating that the conversion results
ADC1006x
ADC1046x
ADC1066x
Device
Family
0
and S
1
Guaranteed
ILE, TUE,
when S/H goes low. Table 1 is a truth table
PSS
-
-
FIGURE 3. Block Diagram of the Multistep Converter Architecture
Guaranteed
Guaranteed
THD, SNR,
ENOB
-
(Continued)
Conversion
900ns
900ns
466ns
Time
Max.
12
are latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S/H and RD are
pull low, INT goes low, indicating that the conversion is
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
TABLE 1. Input Multiplexer Programming
S
0
0
1
1
1
S
0
1
0
ADC10062 (b)
ADC10064 (a)
S
0
1
0
1
0
Channel
V
V
01102014
IN0
IN1
Channel
V
V
V
V
IN0
IN1
IN2
IN3