adc12l063civy National Semiconductor Corporation, adc12l063civy Datasheet - Page 3

• Manufacturer Part Number: adc12l063civy
• Description: 12-bit, 62 Msps, 354 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
31
32
30
10
11
2
3
1
8
Symbol
V
V
CLK
V
V
V
V
OE
PD
REF
IN +
IN −
RM
RP
RN
Equivalent Circuit
3
Non-Inverting analog signal Input. With a 1.0V reference
voltage the input signal level is 1.0 V
Inverting analog signal Input. With a 1.0V reference voltage
the input signal level is 1.0 V
to V
signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 0.8V and 1.2V.
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
Digital clock input. The range of frequencies for this input is 1
MHz to 70 MHz (typical) with guaranteed performance at 62
MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE data output pins. When this pin is high, the
outputs are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
CM
for single-ended operation, but a differential input
Description
P-P
REF
. This pin may be connected
is 1.0V nominal and
P-P
.
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