adc12l063civy National Semiconductor Corporation, adc12l063civy Datasheet - Page 17

• Manufacturer Part Number: adc12l063civy
• Description: 12-bit, 62 Msps, 354 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, V
ended operation, one of the analog inputs should be con-
nected to the d.c. common mode voltage of the driven input.
The peak-to-peak differential input signal should be twice the
reference voltage to maximize SNR and SINAD performance
(Figure 2b). For example, set V
and drive V
very large input signal swings can degrade distortion perfor-
mance, better performance with a single-ended input can be
obtained by reducing the reference voltage when maintain-
ing a full-range output. Tables 1, 2 indicate the input to
output relationship of the ADC12L063.
The V
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702, LMH6628, LMH6622 and LMH6655 are good
amplifiers for driving the ADC12L063.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33Ω series resistors at each of the signal
inputs with a 10 pF capacitor across the inputs, as can be
seen in Figure 5 and Figure 6. These components should be
placed close to the ADC because the input pins of the ADC
is the most sensitive part of the system and this is the last
opportunity to filter the input. The 10 pF capacitor value is for
undersampling application and should be replaced with a
68 pF capacitor for Nyquist application.
2.0 DIGITAL INPUTS
Digital inputs consist of CLK, OE and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 1 MHz to 70 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency is too low, the charge on
internal capacitors can dissipate to the point where the ac-
curacy of the output data will degrade. This is what limits the
lowest sample rate to 1 MSPS.
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
IN +
and the V
REF
IN +
, and be centered around V
with a signal range of 0V to 2.0V. Because
IN −
inputs of the ADC12L063 consist of an
Distortion
REF
to 1.0V, bias V
20026312
(Continued)
CM
. For single
IN −
to 1.0V
17
The CLOCK signal also drives an internal state machine. If
the clock is interrupted, or its frequency is too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12L063 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 35% to 65%.
The clock line should be series terminated in the character-
istic impedance of that line at the clock source. If the clock
line is longer than
where t
signal along the trace. The CLOCK pin should be a.c. termi-
nated with a series RC such that the resistor value is equal
to the characteristic impedance of the clock line and the
capacitor value is
where "I" is the line length in inches and Z
impedance of the clock line. This termination should be
located as close as possible to, but within one centimeter of,
the ADC12L063 clock pin as shown in Figure 4. A typical
propagation rate on FR4 material is about 150ps/inch, or
about 60ps/cm.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12L063 will continue to convert
whether this pin is high or low, but the output can not be read
while the OE pin is high.
2.3 PD
The PD pin, when high, holds the ADC12L063 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down
mode.
3.0 OUTPUTS
The ADC12L063 has 12 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the OE and PD pins are low. While the t
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
r
is the clock rise t
DR
and DR GND. These large charging current
prop
is the propagation rate of the
o
OD
is the characteric
time provides
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