adc122s625eb National Semiconductor Corporation, adc122s625eb Datasheet - Page 6

• Manufacturer Part Number: adc122s625eb
• Description: Adc122s625 Dual 12-bit, 50 Ksps To 200 Ksps, Simultaneous Sampling A/d Converter
• Manufacturer: National Semiconductor Corporation

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Symbol
ADC122S625 Timing Specifications
The following specifications apply for V
noted. Boldface limits apply for T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when the ADC122S625 is operated in a severe fault condition (e.g. when input or output pins
are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: Guaranteed by design, characterization, or statistical analysis and is not tested at final test.
Note 9: While the maximum sample rate is f
Note 10: t
t
CSSU
t
t
t
t
t
t
DIS
DH
CH
EN
DA
CL
t
t
r
f
DIS
CS Setup Time prior to an SCLK rising edge
D
D
D
D
(Note 10)
SCLK High Time
SCLK Low Time
D
D
OUT
OUT
OUT
OUT
OUT
OUT
is the time for D
Enable Time after the falling edge of CS
Hold time after an SCLK Falling edge
Access time after an SCLK Falling edge
Disable Time after the rising edge of CS
Rise Time
Fall Time
OUT
to change 10%.
Parameter
JA
), and the ambient temperature (T
A
SCLK
= T
A
/32, the actual sample rate may be lower than this by having the CS rate slower than f
MIN
= +4.5V to 5.5V, V
to T
J
max) for this device is 150°C. The maximum allowable power dissipation is dictated by T
MAX
: all other limits T
REF
(Note 7)
A
), and can be calculated using the formula P
= 2.5V, f
6
IN
< GND or V
Conditions
A
= 25°C.
SCLK
IN
= 1.6 MHz to 6.4 MHz, C
> V
A
), the current at that pin should be limited to 10 mA. The 50
Typical
1/ f
20
10
4
SCLK
9
9
7
7
D
MAX = (T
L
1/ f
= 25 pF, unless otherwise
Limits
SCLK
20
26
20
25
25
J
7
6
max − T
SCLK
- 3
/32.
A
)/θ
JA
J
max, the
ns (max)
ns (max)
ns (max)
ns (max)
. The values
ns (min)
ns (min)
ns (min)
ns (min)
Units
ns
ns