adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 22

• Manufacturer Part Number: adc1215s125hn/c1
• Description: Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1215S_SER_1
Preliminary data sheet
11.4.2 Equivalent input circuit
11.4.3 Duty cycle stabilizer
11.4.4 Clock input divider
The equivalent circuit of the input clock buffer is shown in
voltage of the differential input stage is set via internal 5 kΩ resistors.
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN =
0), the input clock signal should have a duty cycle of between 45% and 55%.
The ADC1215S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
Fig 18. Equivalent input circuit
20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
CLKM
CLKP
All information provided in this document is subject to legal disclaimers.
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
PACKAGE
Rev. 01 — 12 April 2010
Table
ESD
Table
20), the circuit can handle signals with duty cycles of
20). This feature allows the user to deliver a higher
PARASITICS
ADC1215S series
SE_SEL
Figure
5 kΩ
V
cm(clk)
18. The common-mode
SE_SEL
5 kΩ
© NXP B.V. 2010. All rights reserved.
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