adc0801s040ts NXP Semiconductors, adc0801s040ts Datasheet
adc0801s040ts
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adc0801s040ts Summary of contents
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ADC0801S040 Single 8 bits ADC MHz Rev. 02 — 18 August 2008 1. General description The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from ...
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... DDA I DDD I DDO INL DNL f clk(max) P tot 5. Ordering information Table 2. Ordering information Type number Package Name ADC0801S040TS SSOP20 ADC0801S040_2 Product data sheet Quick reference data = 3 DDD = 1. pF; T i(a)(p-p) L Parameter Conditions analog supply voltage digital supply voltage output supply ...
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... NXP Semiconductors 6. Block diagram V DDA lad VI 9 ANALOG - TO - DIGITAL analog voltage input SSA analog ground Fig 1. Block diagram ADC0801S040_2 Product data sheet CLK 1 CLOCK DRIVER LATCHES CONVERTER Rev. 02 — 18 August 2008 ADC0801S040 Single 8 bits ADC MHz ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol CLK SLEEP V DDD V SSD V DDA V SSA SSO ADC0801S040_2 Product data sheet CLK 1 SLEEP DDD 4 V SSD V 5 DDA ADC0801S V 6 SSA ...
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... NXP Semiconductors Table 3. Symbol DDO 8. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DDA V DDD V DDO i(clk)(p- stg T amb T j [1] The supply voltages V the supply voltage V 9. Thermal characteristics Table 5. Symbol ...
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... NXP Semiconductors Table 6. Characteristics …continued 3 3 DDA DDD = 1. pF typical values measured amb Symbol Parameter V supply voltage difference analog supply current DDA I digital supply current DDD I output supply current DDO P total power dissipation ...
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... NXP Semiconductors Table 6. Characteristics …continued 3 3 DDA DDD = 1. pF typical values measured amb Symbol Parameter Digital outputs and IR (Referenced LOW-level output OL voltage V HIGH-level output OH voltage I OFF-state output current 0.4 V < [1] Clock input CLK ...
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... NXP Semiconductors Table 6. Characteristics …continued 3 3 DDA DDD = 1. pF typical values measured amb Symbol Parameter [7] Differential phase differential phase dif Timing ( MHz pF); see clk L t sampling delay time d(s) t output hold time ...
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... NXP Semiconductors Fig 3. Explanation of 11. Additional information relating to Table 7. Code Underfl 254 255 Overflow Table 8. SLEEP 1 0 ADC0801S040_2 Product data sheet lad 6 RB Table 6 Table note 3 Table 6 Output coding and input voltage (typical values; referenced ...
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... NXP Semiconductors Fig 4. Timing diagram ADC0801S040_2 Product data sheet sample N sample w(clk)L t w(clk)H CLK sample N sample d(s) DATA DATA DATA Rev. 02 — 18 August 2008 ADC0801S040 Single 8 bits ADC MHz sample sample h(o) DATA DATA ...
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... NXP Semiconductors Fig 5. Timing diagram and test conditions of 3-state output delay time 0.291 A (LSB) 0.178 0.065 0.047 0.160 0.272 0 Fig 6. Typical Integral Non-Linearity (INL) performance ADC0801S040_2 Product data sheet V DDD SLEEP output data t dLZ HIGH output data LOW 10 % 3.3 k ADC0801S040 20 pF SLEEP frequency on pin SLEEP = 100 kHz ...
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... NXP Semiconductors 0.150 A (LSB) 0.091 0.032 0.025 0.84 0.143 0 Fig 7. Typical Differential Non-Linearity (DNL) performance Fig 8. Analog input settling-time diagram ADC0801S040_2 Product data sheet 68 136 t s(LH) code 255 code CLK Rev. 02 — 18 August 2008 ADC0801S040 Single 8 bits ADC MHz ...
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... NXP Semiconductors 0 A (dB 120 0 Effective bits: 7.32; THD = 51.08 dB. Harmonic levels (dB): 2nd = 68.99; 3rd = 51.62; 4th = 66.05; 5th = 63.23; 6th = 72.79. Fig 9. Typical fast Fourier transform (f Fig 10. CMOS data outputs V DDO SLEEP V SSO Fig 12. SLEEP 3-state input ADC0801S040_2 Product data sheet 5.0 10 MHz 4.43 MHz) clk i V DDA V DDO ...
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... NXP Semiconductors Fig 14. CLK input ADC0801S040_2 Product data sheet V DDD CLK V SSD Rev. 02 — 18 August 2008 ADC0801S040 Single 8 bits ADC MHz DDD 014aaa507 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 12. Application information 12.1 Application diagrams Fig 15. Application diagram ADC0801S040_2 Product data sheet CLK SLEEP V DDD V SSD V DDA V SSA RB(1) 100 nF RM(1) 100 nF V SSA VI RT(1) V SSA 100 nF V SSA The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value ...
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... NXP Semiconductors 13. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.4 mm 1.5 0.25 0 1.2 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 14. Revision history Table 9. Revision history Document ID Release date ADC0801S040_2 20080818 • Modifications: Corrections made to table notes in • Corrections made to • Corrections made to symbol in • Corrections made to • Corrections made to ADC0801S040_1 20080612 ADC0801S040_2 Product data sheet Data sheet status ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Thermal characteristics Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Additional information relating to 12 Application information 12.1 Application diagrams . . . . . . . . . . . . . . . . . . . 15 13 Package outline ...