stlc1511 STMicroelectronics, stlc1511 Datasheet - Page 19

• Manufacturer Part Number: stlc1511
• Description: Northenlite?? G.lite Bicmos Analog Front-end Circuit
• Manufacturer: STMicroelectronics

Figure 9. Serial Interface Block Diagram
3.6.1 ADC Clip Indicator
Normally, the receive signal level is set such that the
input to the STLC1511 plus the RxPGA gain will not
saturate the input to the ADC converter (for maxi-
mum ADC input levels).
If the input signal is too large however and causes the
F RM C LK
R X S O U T[1:0]
RXSOUT[0]
RXSOUT[1]
FRM CLK
C KDAC
T X S IN [1:0]
TXSIN [0]
TXSIN [1]
CK35M
CK ADC
CK 35M
(4 Dff to align data
edges as required)
2
a5
msb
Q
(x2)
a12
D
a4
2
Q
a11
D
a3
2
a10
a2
S OU T
8-bit Shift Register (x2)
Q
S DATA
CK
a9
a1
D ata clocked out by
D
AD C on this edge
D ATA [15:0]
8-bit Shift Register (x2)
LD
L D
a8
lsb
O U T[15:0]
a7
SD ATA
Data[15:0]
CK
Q
a6
SO U T
ADC to clip, the STLC1511 will report to the digital
chip that a clip has occurred. This is accomplished by
forcing the output data stream supplied to the digital
chip to either “7FFF” hex for an out of range positive
input or to “8000” hex for an out of range negative in-
put. This is highlighted in Figure 10.
Out[15:0]
D
Q
12
msb
b3
14
D
Q
b2
b10
D
Q
Q
b1
(x12)
b9
D
D
b8
lsb
D
Q
(x14)
Q
b7
Q
D
12
D
(4.416MHz Clock from PLL)
(Note: ADC output changes
on posedge of C KADC )
from ADC parallel output
(4.416M Hz Clock from PLL)
D ata sam pled by
D AC on this edge
14
to DAC parallel input
(N ote: DAC input is
sampled on posedge
C KDAC)
b6
CKDAC
CK ADC
b5
b4
STLC1511
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