maxq1004 Maxim Integrated Products, Inc., maxq1004 Datasheet - Page 13

• Manufacturer Part Number: maxq1004
• Description: 1-wire And Spi Authentication Microcontroller
• Manufacturer: Maxim Integrated Products, Inc.

Table 1. Watchdog Interrupt Timeout
The microcontroller has one instance of the 16-bit Timer
0 timer/counter peripheral, which supports the following
functions:
• 13-bit timer/counter
• 16-bit timer/counter
• 8-bit timer with autoreload
• 2 8-bit timer/counters
The integrated SPI is an independent serial communi-
cation channel that communicates synchronously with
peripheral devices in a multiple-master or multiple-slave
system. The interface allows access to a 4-wire, full-
duplex serial bus and can be operated in either master
mode or slave mode. Collision detection is provided
when two or more masters attempt a data transfer at the
same time.
The maximum SPI master transfer rate is Sysclk/2. When
operating as an SPI slave, the device can support up to
Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit
or 16-bit value, MSB first. In addition, the SPI module
supports configuration of an active SSEL state through
the slave active select.
The 1-Wire bus is a system that has a single bus master
and one or more slaves. This microcontroller is always
a slave device in any system. The bus master is typi-
cally another microcontroller. The discussion of this bus
1-Wire and SPI Authentication Microcontroller
PMME
0
0
0
0
1
Serial Peripheral Interface (SPI)
CD[1:0]
00
01
10
11
xx
16-Bit Timer/Counter
Serial Peripherals
1-Wire Bus System
WD[1:0] = 00
2
2
2
2
2
13
14
15
20
12
(1.36ms)
(2.73ms)
(5.46ms)
(175ms)
(683Fs)
WATCHDOG INTERRUPT TIMEOUT (Sysclk = 6MHz)
WD[1:0] = 01
2
2
2
2
15
17
18
2
16
23
(5.46ms)
(21.8ms)
(43.7ms)
(11ms)
iButton is a registered trademark of Maxim Integrated
Products, Inc.
system is broken down into three topics: hardware con-
figuration, transaction sequence, and 1-Wire signaling
(signal types and timing). The 1-Wire protocol defines
bus transactions in terms of the bus state during specific
time slots, which are initiated on the falling edge of sync
pulses from the bus master. Refer to Application Note
937: Book of iButton
description the 1-Wire network and protocols.
The device permits the use of lower 1-Wire voltage levels
(as low as 1.7V) to support the device’s full operating
voltage, but can still be connected to a regular 1-Wire
bus of up to 6V.
The 1-Wire bus has only a single data line (DQ); all
devices on the bus must be able to drive it at the appro-
priate time. This means that each device attached to the
1-Wire bus must have open-drain or high-impedance
outputs. The 1-Wire port is open drain.
Both the standard and overdrive communication speed
of 15.4kbps (max) and 111kbps (max), respectively,
are supported. The value of the pullup resistor primar-
ily depends on the network size and load conditions.
Recommended pullup resistor values can be found in
Table 4-1 of Application Note 937: Book of iButton
Standards.
The idle state for the 1-Wire bus is high. If, for any rea-
son, a transaction needs to be suspended, the bus must
remain in the idle state if the transaction is to resume. If
this does not occur and the bus is left low for more than
120Fs (standard speed), one or more devices on the bus
can be reset.
(1.4s)
WD[1:0] = 10
2
2
2
2
2
18
19
20
21
26
(43.7ms)
(87.4ms)
(175ms)
(350ms)
®
(11.2s)
Standards for a more detailed
Hardware Configuration
WD[1:0] =11
2
2
2
21
22
2
2
29
23
24
(350ms)
(700ms)
(89.5s)
(1.4s)
(2.8s)
13
®