maxq3100-emn Maxim Integrated Products, Inc., maxq3100-emn Datasheet - Page 20

• Manufacturer Part Number: maxq3100-emn
• Description: Maxq3100 Mixed-signal Microcontroller With Analog Comparators, Lcd, And Rtc
• Manufacturer: Maxim Integrated Products, Inc.

The MAXQ3100 generates its internal system clock from
the external 32.768kHz crystal. This serves as the time-
base for the RTC and is multiplied internally by a fre-
quency-locked loop (FLL) to provide a system clock of
4.194MHz. Best performance is achieved when mated
with a 32.768kHz crystal rated for a 6pF load. No exter-
nal load capacitors are required. The frequency accura-
cy of a crystal-based oscillator circuit is dependent upon
crystal accuracy, the match between the crystal and the
oscillator capacitor load, ambient temperature, etc.
A crystal warmup counter enhances operational reliabili-
ty. Each time the external crystal oscillation must restart,
including a power-on reset, the device initiates a crystal
warmup period of approximately 2 seconds. This warmup
period allows time for the crystal amplitude and frequen-
cy to stabilize before using it as a clock source.
Advanced power-management features minimize power
consumption by dynamically matching the processing
speed of the device to the required performance level.
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Figure 2. Clock Sources
20
POWER-ON
______________________________________________________________________________________
RESET
STOP
INPUT
ENABLE
LOCKED LOOP
FREQUENCY-
OSCILLATOR
CRYSTAL
32kHz
Power Management
X32RY
FLLRY
4-CYCLE
System Timing
DELAY
RESET
CLK INPUT
STARTUP
TIMER
XDOG
MAXQ3100
DIVIDER
CLOCK
XDOG DONE
SELECTOR
This means device operation can be slowed and power
consumption minimized during periods of reduced
activity. When more processing power is required, the
microcontroller can increase its operating frequency.
Software-selectable clock-divide operations allow flexi-
bility, selecting whether a system clock cycle (SYSCLK)
is 1, 2, 4, or 8 of the 4.194MHz oscillator cycles. By per-
forming this function in software, a lower power state
can be entered without the cost of additional hardware.
For extremely power-sensitive applications, two addi-
tional low-power modes are available.
• Divide-by-256 power-management mode (PMM1)
• Stop mode (STOP = 1)
In PMM1, one system clock is 256 oscillator cycles, sig-
nificantly reducing power consumption while the micro-
controller functions at reduced speed. The optional
switchback feature allows enabled interrupt sources,
such as the external interrupts, to cause the processor to
quickly exit PMM1 mode and return to a faster internal
clock rate.
DEFAULT
(PMME = 1, CD1:0 = 00b)
ENABLE
GENERATION
WATCHDOG
CLOCK
TIMER
RESET DOG
WATCHDOG DONE
RWT
RESET
WATCHDOG RESET
WATCHDOG INTERRUPT
SYSTEM CLOCK
SWB
SWITCHBACK SOURCE
RESET
STOP
STOP
POWER-ON
RESET