max5523euat Maxim Integrated Products, Inc., max5523euat Datasheet - Page 13

• Manufacturer Part Number: max5523euat
• Description: Dual, Ultra-low-power, 10-bit, Voltage-output Dacs
• Manufacturer: Maxim Integrated Products, Inc.

The MAX5522–MAX5525 dual, 10-bit, ultra-low-power,
voltage-output DACs offer rail-to-rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA (max) The MAX5523/MAX5525 include an inter-
nal reference that saves additional board space and
can source up to 8mA, making it functional as a system
reference. The 16MHz, 3-wire serial interface is com-
patible with SPI, QSPI, and MICROWIRE protocols.
When V
zero scale with virtually no output glitch. The MAX5522/
MAX5523 output buffers are configured in unity gain
and come in µMAX packages. The MAX5524/MAX5525
output buffers are configured in force sense allowing
users to externally set voltage gains on the output (an
output-amplifier inverting input is available). The
MAX5524/MAX5525 come in 4mm x 4mm thin QFN
packages.
DD
is applied, all DAC outputs are driven to
______________________________________________________________________________________
SCLK
DIN
CS
Detailed Description
CONTROL
CONTROL
REGISTER
POWER-
DOWN
LOGIC
SHIFT
AND
REGISTER
REGISTER
INPUT
INPUT
10-Bit, Voltage-Output DACs
PROGRAMMABLE
V
DD
GND
REFERENCE
2-BIT
REGISTER
REGISTER
DAC
DAC
The MAX5522–MAX5525 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5522–MAX5525 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. The 16 bits consist of 4 control bits
(C3–C0), 10 data bits (D9–D0) (Table 1), and 2 sub-bits
(S1 and S0). D9–D0 are the DAC data bits and S1 and
S0 are the sub-bits. The sub-bits must be set to zero for
proper operation. Following the control bits, data loads
MSB first, D9–D0. The control bits C3–C0 control the
MAX5522–MAX5525, as outlined in Table 2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
Dual, Ultra-Low-Power,
Loading the input registers without updating the DAC
registers
Updating the DAC registers from the input registers
Updating all the input and DAC registers simultaneously
Functional Diagrams (continued)
BUF
REF
10-BIT DAC
10-BIT DAC
MAX5525
REFOUT
OUTA
FBA
OUTB
FBB
Digital Interface
13