m48t37v STMicroelectronics, m48t37v Datasheet - Page 17

• Manufacturer Part Number: m48t37v
• Description: 5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

3.7
3.8
3.9
Note:
Note:
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog
Register or an edge transition (low to high / high to low) on the WDI pin occurs. The time-out
period then starts over.
The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the
Watchdog Register. Should the watchdog timer time-out, a value of 00h needs to be written
to the Watchdog Register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied. The WDI pin should be connected to V
Power-on reset
The M48T37Y/V continuously monitors V
point, the RST pulls low (open drain) and remains low on power-up for t
passes V
an appropriate resistor to V
page
Programmable Interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an
interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the Flag Register
7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the Watchdog Steering
(WDS) Bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.
The Alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register. An
interrupt condition reset will not occur unless the addresses are stable at the flag location for
at least 15ns while the device is in the READ Mode as shown in
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10k
recommended) to V
occurs or the Frequency Test Mode is enabled.
Battery low flag
The M48T37Y/V automatically performs periodic battery voltage monitoring upon power-up.
The Battery Low Flag (BL), Bit D4 of the Flags Register 7FF0h, will be asserted high if the
SNAPHAT
active until completion of battery replacement and subsequent battery low monitoring tests
during the next power-up sequence.
If a battery low is generated during a power-up sequence, this indicates the battery voltage
is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data
should be considered suspect and verified as correct. A fresh battery should be installed.
The SNAPHAT top may be replaced while VCC is applied to the device.
This will cause the clock to lose time during the interval the battery/crystal is removed.
Battery monitoring is a useful technique only when performed periodically. The M48T37Y/V
only monitors the battery when a nominal V
22).
PFD
®
battery is found to be less than approximately 2.5V. The BL Flag will remain
. RST is valid for all V
CC
. The pin remains in the high impedance state unless an interrupt
CC
should be chosen to control rise time (see
CC
conditions. The RST pin is an open drain output and
CC
CC
. When V
is applied to the device. Thus applications
CC
falls to the power fail detect trip
Figure 7 on page
REC
SS
Figure 13 on
if not used.
after V
14.
CC
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