m41st84w STMicroelectronics, m41st84w Datasheet - Page 7

• Manufacturer Part Number: m41st84w
• Description: 3.0/3.3v I 2c Serial Rtc With Supervisory Functions
• Manufacturer: STMicroelectronics

OPERATING MODES
The M41ST84W clock operates as a slave device
on the serial bus. Access is obtained by imple-
menting a start condition followed by the correct
slave address (D0h). The 64 bytes contained in
the device can then be accessed sequentially in
the following order:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11 - 16. Alarm Registers
17 - 19. Reserved
20.
21 - 64. User RAM
The M41ST84W clock continually monitors V
for an out-of tolerance condition. Should V
below V
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
and the power supply is switched to external V
Write protection continues until V
V
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
–
–
CC
PFD
Data transfer may be initiated only when the
bus is not busy.
During data transfer, the data line must remain
stable whenever the clock line is High.
rises above V
(min) plus t
CC
PFD
Tenths/Hundredths of a Second Register
Seconds Register
Minutes Register
Century/Hours Register
Day Register
Date Register
Month Register
Year Register
Control Register
Watchdog Register
Square Wave Register
falls below V
, the device terminates an access in
rec
SO
(min).
, the battery is disconnected,
SO
, the device automati-
CC
reaches
CC
CC
fall
CC
.
–
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Changes in the data line, while the clock line is
High, will be interpreted as control signals.
M41ST84W
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