m41t256y STMicroelectronics, m41t256y Datasheet - Page 12

• Manufacturer Part Number: m41t256y
• Description: 256 Kbit 32k X8 Serial Rtc
• Manufacturer: STMicroelectronics

Figure 6.
Table 2.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL
2.2
12/30
t
Symbol
SU:DAT
t
t
t
t
SU:STO
HD:DAT
HD:STA
SU:STA
t
t
t
f
HIGH
LOW
SCL
BUF
t
t
R
F
(2)
SDA
SCL
Bus timing requirements sequence
AC characteristics
Read mode
In this mode the master reads the M41T256Y slave after setting the slave address (see
Figure 7 on page
Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of
address byte A(0) is a “Don’t care”). Next the START condition and slave address are
repeated followed by the READ mode control bit (R/W=1). At this point the master
transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter.
The address pointer is only incremented on reception of an acknowledge clock. The
M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the
SCL clock frequency
Time the bus must be free before a new transmission can
start
SDA and SCL fall time
Data hold time
START condition hold time
(after this period the first clock pulse is generated)
Clock high period
Clock low period
SDA and SCL rise time
Data setup time
START condition setup time
(only relevant for a repeated start condition)
STOP condition setup time
tBUF
P
S
13). Following the WRITE mode control bit (R/W=0) and the Acknowledge
tHD:STA
tR
A
Parameter
= –25 to 70°C; V
tLOW
tHIGH
tF
(1)
CC
= 4.5 to 5.5V (except where noted).
tHD:DAT
tSU:DAT
SR
Min
600
600
100
600
600
1.3
1.3
tSU:STA
0
0
tHD:STA
Max
400
300
300
P
AI00589
tSU:STO
Unit
kHz
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns