pca85232 NXP Semiconductors, pca85232 Datasheet - Page 40

• Manufacturer Part Number: pca85232
• Description: Pca85232 Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA85232
Product data sheet
Table 21.
In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is
connected to V
the CLK pin. The other PCA85232 devices are having the OSC pin connected to V
meaning that these devices are ready to receive external clock, the signal being provided
by the device with subaddress 0.
In the case that the master is providing the clock signal to the slave devices, care must be
taken that the sending of display enable or disable will be received by both, the master
and the slaves at the same time. When the display is disabled the output from pin CLK is
disabled too. The disconnection of the clock may result in a DC component for the display.
Alternatively, the schematic can be also constructed such that all the devices have OSC
pin connected to V
connected to the same external CLK).
A configuration where SYNC is connected but all PCA85232 are using the internal clock
(OSC pin tied to V
Number of devices
2
3 to 5
6 to 8
SYNC contact resistance
SS
All information provided in this document is subject to legal disclaimers.
so that this device uses its internal clock to generate a clock signal at
SS
DD
) is not recommended and may lead to display artifacts!
and thus an external CLK being provided for the system (all devices
Rev. 1 — 8 December 2010
Maximum contact resistance
6000 Ω
2200 Ω
1200 Ω
LCD driver for low multiplex rates
PCA85232
© NXP B.V. 2010. All rights reserved.
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