pcf8833 NXP Semiconductors, pcf8833 Datasheet - Page 87

• Manufacturer Part Number: pcf8833
• Description: Stn Rgb - 132 X 132 X 3 Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
15.5
Table 94 contains a list of all OTP related commands.
Table 94 OTP related commands
Note
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be 0.
15.5.1
When CALMM = 1 the device enters the calibration
module maker mode. This mode enables the filling of the
OTP matrix and allows programming of the non-volatile
OTP cells to take place.
The V
cells, but through a switch that must be closed for
programming by setting OPE to logic 1.
The OTP row to be programmed may be chosen by setting
the OTP row address ORA[2:0].
15.5.2
The action of the refresh instruction is to force the registers
of the OTP matrix to load the value from the non-volatile
part of the OTP cell. This instruction takes up to 1 ms to
complete. During this time all other instructions may be
sent.
In the PCF8833 the refresh instruction is associated with
the Sleep_OUT instruction such that the shift register is
automatically refreshed every time the Sleep_OUT
instruction is sent.
No refresh may be started when in CALMM mode, i.e.
whenever CALMM = 1.
2003 Feb 14
CALMM
Sleep_OUT
OTPSHTIN
SFD
STN RGB - 132
NAME
OTP(drain)
Interface commands
C
R
ALIBRATION MODULE MAKER MODE
EFRESH
pad is not connected directly to the OTP
D/C
0
1
0
0
1
0
D7
X
X
1
0
1
1
D6
D
X
1
0
1
1
132
6
ORA
D5
D
1
0
1
1
5
2
3 driver
COMMAND BYTE
ORA
D4
D
1
1
1
0
4
1
ORA
D3
D
0
0
0
1
3
0
87
D2
D
X
0
0
0
1
(1)
2
15.5.3
The OTP matrix (see Table 90) is filled using the
OTPSHTIN command, which is similar to the RAM write
command. First the appropriate command is sent, then the
following data bytes are shifted bytewise into the OTP
matrix from left to right, i.e. the new byte is loaded into
byte 0, whereas the data of byte 0 is shifted into byte 1 and
so on. Bit 7 of the data is not used. The shifting is enabled
as long as D/C remains at logic 1.
15.6
In order to calibrate the programming of V
sequence in Table 95 is suggested to determine what
MMVOP value has to be programmed.
It is assumed that the relevant parameters, the V
programming, V
the interface. This implies that SFD is set to logic 0 and
that all OTP settings except MMVOP are ignored.
OPE
D1
D
0
0
0
1
1
Suggestion on how to calibrate V
MMVOP
S
CALMM
HIFT IN
SFD
D0
D
0
1
1
0
PR
and the number of stages S, are set via
EE/EF set factory default (see
HEX
F0
11
F1
Sections 6.2.47 and 15.2)
CALMM command
entry CALMM mode
(CALMM) enable
programming (OPE) set
address (ORA)
generate a refresh of the
OTP if CALMM = 0
start shifting data in the shift
register; the shifting is
executed as long as D/C = 1
DESCRIPTION
Objective specification
PCF8833
LCD2
LCD2
, the
using
LCD2