pcf8812 NXP Semiconductors, pcf8812 Datasheet - Page 10

• Manufacturer Part Number: pcf8812
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10 INSTRUCTIONS
The instruction format is divided into two modes: If pad D/C
(data or command select) is set LOW the current byte is
interpreted as a command (see Table 1). The general
format of the data stream is shown in Fig.7. If pad D/C is
set HIGH the data bytes that follow are stored in the
display data RAM. After every data byte the address
counter is incremented automatically. The level of the
D/C signal is read during the last bit period of each data
byte. Each instruction can be sent to the PCF8812 in any
order. The MSB of a byte is transmitted first. One possible
command stream used to set-up the LCD driver is shown
in Fig.8. The serial interface is initialized when pad SCE is
HIGH. In this state SCLK clock pulses have no effect and
no power is consumed by the serial interface. A negative
edge on pad SCE enables the serial interface and
indicates the start of a data transmission.
Figures 9 and 10 show the serial bus protocol for the
transmission of one byte and several bytes respectively:
2004 Feb 23
handbook, full pagewidth
When pad SCE is HIGH, SCLK clock pulses are ignored
and the serial interface is initialized
SDIN is sampled at the positive edge of SCLK
65
102 pixels matrix LCD driver
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
102
204
306
408
510
612
714
816
0
0
103
205
307
409
511
613
715
817
1
104
206
308
410
512
614
716
818
2
X address
10
Pad D/C indicates whether the byte is a command
(pad D/C = 0) or RAM data (pad D/C = 1). The state of
D/C is read during the eighth SCLK pulse period
If pad SCE stays LOW after the last bit of a command or
data byte, the serial interface expects bit DB7 of the next
byte at the next positive edge of SCLK (see Fig.11).
If pad SCLK goes LOW after the last data bit (bit DB0),
either:
– A rising clock edge is required to latch the last data bit
– Or the last bit is latched when pad SCE goes HIGH
You can set the address pointer to a specific address,
using the appropriate commands, at any time
(see Table 1). A special case is when the current
address pointer location is at the last address (x101 and
y8). In this case you must send a No Operation
Command (NOP) before setting the new address.
A reset pulse RES interrupts the transmission. No data
is written into the RAM and the registers are cleared.
If pad SCE is LOW after the positive edge of pad RES,
the serial interface is ready to receive bit 7 of a
command or data byte as shown in Fig.11.
(see Fig.12).
917
101
Y address
0
8
MGS396
Product specification
PCF8812