pcf8534a NXP Semiconductors, pcf8534a Datasheet - Page 17

• Manufacturer Part Number: pcf8534a
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8534A_3
Product data sheet
7.12 Subaddress counter
7.13 Output bank selector
7.14 Input bank selector
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed only when the contents of the subaddress counter agree with the
hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined
by the device select command (see
and the hardware subaddress do not agree then data storage is blocked but the data
pointer will be incremented as if data storage had taken place.
In cascaded applications each PCF8534A in the cascade must be addressed separately.
Initially, the first PCF8534A is selected by sending the device select command matching
the first device's hardware subaddress. Then the data pointer is set to the preferred
display RAM address by sending the load data pointer command.
Once the display RAM of the first PCF8534A has been written, the second PCF8534A is
selected by sending the device select command again. This time however the command
matches the second device's hardware subaddress. Next the load data pointer command
is sent to select the preferred display RAM address of the second PCF8534A.
This last step is very important because during writing data to the first PCF8534A, the
data pointer of the second PCF8534A is incremented. In addition, the hardware
subaddress should not be changed whilst the device is being accessed on the I
interface.
The output bank selector (see
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
The SYNC signal resets these sequences to the following starting points: bit 3 for
1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode.
The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In static drive mode, the bank select command may request the contents of
bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode,
the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables
preparation of display information in an alternative bank and the ability to switch to it once
it has been assembled.
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. Using the bank select command, display data can be loaded in
bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank
selector functions independently to the output bank selector.
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In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.
In 1:2 multiplex mode: bits 0 and 1 are selected.
In the static mode: bit 0 is selected.
Rev. 03 — 10 November 2008
Table
Table
13), selects one of the four bits per display RAM
12). If the contents of the subaddress counter
Universal LCD driver for low multiplex rates
PCF8534A
© NXP B.V. 2008. All rights reserved.
2
C-bus
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