pcf8576d NXP Semiconductors, pcf8576d Datasheet - Page 17

• Manufacturer Part Number: pcf8576d
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

Philips Semiconductors
In the 1 : 4 mode, the eight transmitted data bits are
placed in bits 0, 1, 2 and 3 of two successive display RAM
addresses.
6.11
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
6.12
The storage of display data is determined by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place. The
subaddress counter is also incremented when the data
pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576D occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 mode).
The hardware subaddress should not be changed whilst
the device is being accessed on the I
2004 Dec 22
Universal LCD driver for low
multiplex rates
Fig.11 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
Data pointer
Subaddress counter
and between bits in a RAM word and backplane outputs.
backplane outputs
display RAM bits
(columns) /
(BP)
0
1
2
3
2
0
C-bus interface.
1
2
display RAM addresses (rows) / segment outputs (S)
3
4
17
arriving data byte is stored at the display RAM address
indicated by the data pointer in accordance with the filling
order shown in Fig.12. After each byte is stored, the
contents of the data pointer are automatically incremented
by a value dependent on the selected LCD drive mode:
eight (static drive mode), four (1 : 2 mode), three
(1 : 3 mode) or two (1 : 4 mode). If an I
is terminated early then the state of the data pointer will be
unknown. The data pointer should be re-written prior to
further RAM accesses.
6.13
The output bank selector selects one of the four bits per
display RAM address for transfer to the display latch. The
actual bit chosen depends on the selected LCD drive
mode and on the instant in the multiplex sequence. In 1 : 4
mode, all RAM addresses of bit 0 are selected, these are
followed by the contents of bit 1, bit 2 and then bit 3.
Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected
sequentially. In 1 : 2 mode, bits 0 and 1 are selected and,
in static mode, bit 0 is selected. Signal SYNC will reset
these sequences to the following starting points; bit 3 for
1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and
bit 0 for static mode.
The PCF8576D includes a RAM bank switching feature in
the static and 1 : 2 drive modes. In the static drive mode,
the BANK SELECT command may request the contents of
bit 2 to be selected for display instead of the contents of
bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be
selected instead of bits 0 and 1. This allows display
information to be prepared in an alternative bank and then
selected for display when it is assembled.
Output bank selector
35
36
37
38
MBE525
39
Product specification
2
PCF8576D
C-bus data access