74lv574db NXP Semiconductors, 74lv574db Datasheet - Page 2

• Manufacturer Part Number: 74lv574db
• Description: Octal D-type Flip-flop; Positive Edge-trigger 3-state
• Manufacturer: NXP Semiconductors

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING AND PACKAGE INFORMATION
PIN DESCRIPTION
t
f
C
C
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
PIN NUMBER
1
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10
11
20
1998 Jun 10
PHL
max
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Common 3-State output enable input
Output capability: bus driver
I
Octal D-type flip-flop; positive edge-trigger (3-State)
I
PD
CC
P
f
f
S (C
amb
amb
i
o
PD
D
= input frequency in MHz; C
SYMBOL
/t
= output frequency in MHz; V
category: MSI
PLH
= C
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PACKAGES
PD
OLP
OHV
V
amb
CC
(output ground bounce) t 0.8V at V
(output V
V
2
= 25 C; t
CC
SYMBOL
OE
D0–D7
Q0–Q7
GND
CP
VCC
2
f
I
Propagation delay
CP to Q
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
o
x f
= GND to V
) = sum of the outputs.
i
OH
r
)S (C
=t
undershoot) u 2V at V
f
n
v2.5 ns
FUNCTION
Output enabled input (active LOW)
Data inputs
3-State flip-flop outputs
Ground (0V)
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
TEMPERATURE RANGE
L
L
CC
= output load capacity in pF;
CC
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
PARAMETER
V
CC
= supply voltage in V;
CC
2
= 2.7V and V
f
o
) where:
CC
CC
CC
= 3.3V,
= 3.3V,
= 3.6V
D
in W)
OUTSIDE NORTH
74LV574 PW
74LV574 DB
C
V
C
Notes 1 and 2
74LV574 N
74LV574 D
AMERICA
CC
L
L
= 15pF
= 15pF, V
2
= 3.3V
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE) input
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
FUNCTION TABLE
H
h
L
l
Z
CONDITIONS
Load register and
disable outputs
Load and read
OPERATING
CC
MODES
register
= HIGH voltage level
= HIGH voltage level one set-up time prior to the
= LOW voltage level
= LOW voltage level one set-up time prior to the
= High impedance OFF-state
= LOW–to–HIGH clock transition
= 3.3V
LOW-to-HIGH CP transition
LOW-to-HIGH CP transition
NORTH AMERICA
74LV574PW DH
74LV574 DB
74LV574 N
74LV574 D
OE
H
H
L
L
INPUTS
CP
TYPICAL
Dn
h
h
l
l
3.5
13
77
25
FLIP-FLOPS
INTERNAL
Product specification
H
H
L
L
PKG. DWG. #
74LV574
SOT146-1
SOT163-1
SOT339-1
SOT360-1
853-1990 19545
OUTPUTS
UNIT
MHz
Q0 to Q7
ns
pF
pF
H
L
Z
Z