74lv377db NXP Semiconductors, 74lv377db Datasheet - Page 2

• Manufacturer Part Number: 74lv377db
• Description: Octal D-type Flip-flop With Data Enable; Positive Edge-trigger
• Manufacturer: NXP Semiconductors

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
PIN DESCRIPTION
t
f
C
C
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
1
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10
11
20
1998 Jun 10
PHL
max
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Ideal for addressable register applications
Data enable for address and data synchronization applications
Eight positive-edge triggered D-type flip-flops
Output capability: standard
I
Octal D-type flip-flop with data enable;
positive edge-trigger
I
PD
CC
NUMBER
P
f
f
S (C
amb
amb
i
o
PD
D
= input frequency in MHz; C
SYMBOL
/t
= output frequency in MHz; V
category: MSI
PIN
PLH
= C
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PD
OLP
OHV
V
amb
PACKAGES
CC
(output ground bounce) t 0.8V @ V
(output V
V
2
= 25 C; t
CC
SYMBOL
Q
D
2
0
0
GND
f
I
V
Propagation delay
CP to Q
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
o
CP
= GND to V
to Q
to D
E
) = sum of the outputs.
CC
OH
f
r
i
7
7
)S (C
= t
undershoot) u 2V @ V
f
n
v2.5 ns
Data enable input (active-LOW)
flip-flop outputs
Data inputs
Ground (0V)
Clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
L
L
CC
= output load capacity in pF;
CC
PARAMETER
CC
V
= supply voltage in V;
TEMPERATURE RANGE
CC
= 2.7V and V
2
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
FUNCTION
f
o
) where:
CC
CC
CC
= 3.3V,
= 3.3V,
= 3.6V
D
in W)
C
V
V
Notes 1 and 2
OUTSIDE NORTH AMERICA
CC
L
= 15pF
2
= 3.3V
3 3V
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Q
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
FUNCTION TABLE
H
h
L
l
X
74LV377 PW
74LV377 DB
CONDITIONS
74LV377 N
74LV377 D
OPERATING MODES
OPERATING MODES
Hold (do nothing)
= HIGH voltage level
= HIGH voltage level one set-up time prior to the
= LOW voltage level
= LOW voltage level one set-up time prior to the
= LOW–to–HIGH CP transition
= Don’t care
Load ‘‘1’’
Load ‘‘0’’
LOW-to-HIGH CP transition
LOW-to-HIGH CP transition
NORTH AMERICA
74LV377PW DH
74LV377 DB
CP
74LV377 N
74LV377 D
X
TYPICAL
INPUTS
3.5
13
77
20
H
E
h
l
l
D
Product specification
X
X
h
l
n
74LV377
853–1935 19545
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
OUTPUTS
No change
No change
UNIT
MHz
Q
ns
pF
pF
H
L
n
n
) of