74lv132db NXP Semiconductors, 74lv132db Datasheet

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74lv132db

Manufacturer Part Number
74lv132db
Description
Quad 2-input Nand Schmitt-trigger
Manufacturer
NXP Semiconductors
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LV132DB
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74lv132db,118
Manufacturer:
NEXPERIA/安世
Quantity:
20 000
1. General description
2. Features
3. Applications
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals.
They are capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
input hysteresis voltage V
74LV132
Quad 2-input NAND Schmitt trigger
Rev. 04 — 12 November 2007
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
amb
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
H
.
CC
OH
T+
) undershoot: > 2 V at V
= 2.7 V and V
and the negative voltage V
CC
= 3.3 V and T
CC
= 3.6 V
amb
= 25 C
CC
Product data sheet
= 3.3 V and
T
is defined as the

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74lv132db Summary of contents

Page 1

Quad 2-input NAND Schmitt trigger Rev. 04 — 12 November 2007 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV132N +125 C 74LV132D +125 C 74LV132DB +125 C 74LV132PW +125 C 74LV132BQ +125 C 5. Functional diagram ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 132 GND 001aac203 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 6.2 Pin description Table 2. Pin description Symbol Pin GND ...

Page 4

... NXP Semiconductors 7. Functional description Table 3. Function table H = HIGH voltage level LOW voltage level. Input Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter [1] V supply voltage CC V input voltage I V output voltage O T ambient temperature amb [1] The static characteristics are guaranteed from 1.0 V (with input levels GND ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation delay nA nY; see power dissipation capacitance V = GND [1] All typical values are measured at T ...

Page 7

... NXP Semiconductors Table 8. Measurement points Supply voltage V CC < 2 3.6 V 4.5 V Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load resistance Load capacitance including jig and probe capacitance. L Fig 7. Load circuit for switching times Table 9 ...

Page 8

... NXP Semiconductors Table 10. Transfer characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions V negative-going see T threshold voltage hysteresis voltage ( [1] All typical values are measured ...

Page 9

... NXP Semiconductors 0 Fig 10. Typical 74LV132 transfer characteristics Fig 12. Typical 74LV132 transfer characteristics 74LV132_4 Product data sheet 001aaa659 100 0.9 1.2 V (V) I Fig 11. Typical 74LV132 transfer characteristics 300 200 100 0 0 0.6 1.2 1.8 Rev. 04 — 12 November 2007 ...

Page 10

... NXP Semiconductors 15. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 15 ...

Page 13

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... Document ID Release date 74LV132_4 20071112 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Transfer characteristics Waveforms transfer characteristics ...

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