74lvc1g175gw NXP Semiconductors, 74lvc1g175gw Datasheet - Page 9

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74lvc1g175gw

Manufacturer Part Number
74lvc1g175gw
Description
Single D-type Flip-flop With Reset; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet

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12. Waveforms
74LVC1G175_3
Product data sheet
Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to
Fig 8. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width, and the MR to
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
D hold times, and the maximum clock pulse frequency
Measurement points are given in
V
CP recovery time
OL
OL
and V
and V
OH
OH
are typical output voltage drops that occur with the output load.
are typical output voltage drops that occur with the output load.
MR input
CP input
Q output
CP input
Q output
D input
GND
GND
GND
GND
V
V
V
V
OH
OH
OL
OL
V
V
V
V
Table
Table
I
I
I
I
9.
9.
V
M
Rev. 03 — 21 May 2007
t
su
t
V
h
V
M
Single D-type flip-flop with reset; positive-edge trigger
M
t
V
PHL
t
W
M
t
PHL
t
W
1/f
max
V
M
t
su
t
rec
t
V
h
M
001aaa464
001aaa465
t
PLH
74LVC1G175
© NXP B.V. 2007. All rights reserved.
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