74lvc1g175gw NXP Semiconductors, 74lvc1g175gw Datasheet - Page 3

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74lvc1g175gw

Manufacturer Part Number
74lvc1g175gw
Description
Single D-type Flip-flop With Reset; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
6. Pinning information
Table 3.
7. Functional description
Table 4.
[1]
74LVC1G175_3
Product data sheet
Symbol
CP
GND
D
Q
V
MR
Operating mode
Reset (clear)
Load ‘1’
Load ‘0’
Fig 4. Pin configuration SOT363
CC
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care.
= LOW-to-HIGH CP transition;
GND
CP
D
and SOT457
Pin description
Function table
1
2
3
74LVC1G175
6.1 Pinning
6.2 Pin description
001aag506
Pin
1
2
3
4
5
6
[1]
6
5
4
Input
MR
L
H
H
MR
V
Q
CC
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
data input
flip-flop output
supply voltage
master reset input (active LOW)
Fig 5. Pin configuration SOT886
GND
Rev. 03 — 21 May 2007
CP
D
CP
X
Transparent top view
74LVC1G175
1
2
3
Single D-type flip-flop with reset; positive-edge trigger
001aag507
6
5
4
MR
V
Q
CC
D
X
h
l
Fig 6. Pin configuration SOT891
GND
CP
74LVC1G175
D
Transparent top view
74LVC1G175
1
2
3
Output
Q
L
H
L
© NXP B.V. 2007. All rights reserved.
001aag508
6
5
4
MR
V
Q
CC
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